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PDF W25Q32V Data sheet ( Hoja de datos )
| Número de pieza | W25Q32V | |
| Descripción | 32M-BIT SERIAL FLASH MEMORY | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W25Q32V
32M-BIT
SERIAL FLASH MEMORY WITH
DUAL AND QUAD SPI
www.DataSheet.net/
-1-
Publication Release Date: August 19, 2009
Preliminary - Revision E
Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
W25Q32V
1. GENERAL DESCRIPTION
The W25Q32V (32M-bit) Serial Flash memory provides a storage solution for systems with limited space,
pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current
consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving
packages.
The W25Q32V array is organized into 16,384 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB
block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32V has 1,024
erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in
applications that require data and parameter storage. (See figure 2.)
The W25Q32V supports the standard Serial Peripheral Interface (SPI), and a Dual/Quad output as well
as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2 (/WP), and I/O3
(/HOLD). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz
for Dual Output and 320MHz for Quad Output when using the Fast Read Dual/Quad Output instructions.
These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The
Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-
overhead to read a 24-bit address, allowing true XIP (execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification with a 64-bit Unique Serial Number.
2. FEATURES
Family of SpiFlash Memories
– W25Q32: 32M-bit / 4M-byte (4,194,304)
– 256-bytes per programmable page
Standard, Dual or Quad SPI
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
Highest Performance Serial Flash
– Up to 6X that of ordinary Serial Flash
– 80MHz clock operation
– 160MHz equivalent Dual SPI
– 320MHz equivalent Quad SPI
– 40MB/S continuous data transfer rate
Efficient “Continuous Read Mode”
– Low Instruction overhead
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
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Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, <1µA Power-down (typ.)
– -40°C to +85°C operating range
Flexible Architecture with 4KB sectors
– Uniform Sector Erase (4K-bytes)
– Block Erase (32K and 64K-bytes)
– Program one to 256 bytes
– More than 100,000 erase/write cycles
– More than 20-year data retention
Advanced Security Features
– Software and Hardware Write-Protect
– Top or Bottom, Sector or Block selection
– Lock-Down and OTP protection(1)
– 64-Bit Unique ID for each device(1)
Space Efficient Packaging
– 8-pin SOIC 208-mil
– 8-pad WSON 6x5-mm / (2)8x6-mm
– 16-pin SOIC 300-mil
– Contact Winbond for KGD and CSP options
(1)Contact Winbond for details
(2)Special Order, contact Winbond for more ordering information.
Publication Release Date: August 19, 2009
- 5 - Preliminary - Revision E
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
W25Q32V
9.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern the W25Q32V
provides several means to protect data from inadvertent writes.
9.2.1 Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after program and erase
Software and Hardware (/WP pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection until next power-up(1)
One Time Program (OTP) write protection(1)
Note 1: These features are available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q32V will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 29). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
www.DataSheet.net/
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a program,
erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled state
of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting
the Status Register Protect (SRP0, SRP1) and Block Protect (SEC,TB, BP2, BP1 and BP0) bits. These
settings allow a portion or all of the memory to be configured as read only. Used in conjunction with the
Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under hardware
control. See Status Register for further information. Additionally, the Power-down instruction offers an
extra level of write protection as all instructions are ignored except for the Release Power-down
instruction.
- 11 -
Publication Release Date: August 19, 2009
Preliminary - Revision E
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W25Q32V.PDF ] | |
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