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PDF UPD720102 Data sheet ( Hoja de datos )
| Número de pieza | UPD720102 | |
| Descripción | USB 2.0 HOST CONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
μPD720102
USB 2.0 HOST CONTROLLER
The μPD720102 complies with the universal serial bus specification revision 2.0 and open host controller interface
specification for full-/low-speed signaling and Intel's enhanced host controller interface specification for high-speed
signaling and works up to 480 Mbps. The μPD720102 is integrated 2 host controller cores with PCI interface and USB
2.0 transceivers into a single chip.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
μPD720102 User’s Manual: S17999E
FEATURES
• Compliant with universal serial bus specification revision 2.0 (data rate: 1.5/12/480 Mbps)
• Compliant with open host controller interface specification for USB release 1.0a
• Compliant with enhanced host controller interface specification for USB revision 1.0
• PCI multi-function device consists of one OHCI host controller core for full-/low-speed signaling and one EHCI host
controller core for high-speed signaling
• Root hub with 3 (Max.) downstream facing ports which are shared by OHCI and EHCI host controller cores
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• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)
transaction
• Supports hyper-speed transfer mode using HSMODE signal
• 32-bit 33 MHz host interface compliant with PCI specification revision 2.2
• Supports PCI mobile design guide version 1.1
• Supports PCI-bus power management interface specification revision 1.1
• PCI bus bus-master access
• Supports 3.3 V PCI
• System clock is generated by 30 MHz crystal or 48 MHz clock input
• Operational registers direct-mapped to PCI memory space
• 3.3 V single power supply, 1.5 V internal operating voltage from on chip regulator
• On chip Rs and Rpd resistors for USB signals
ORDERING INFORMATION
Part Number
Package
Remark
μPD720102GC-YEB-A 120-pin plastic TQFP (fine pitch) (14 × 14) Lead-free product
<R> μPD720102F1-CA7-A 121-pin plastic FBGA (8 × 8)
Lead-free product
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S17998EJ4V0DS00 (4th edition)
Date Published March 2007 NS CP (N)
Printed in Japan
The mark "<R>" shows major revised points.
2006Datasheet pdf - http://www.DataSheet4U.co.kr/
1 page  
μPD720102
Pin Name
• 120-pin plastic TQFP (fine pitch) (14 × 14)
μPD720102GC-YEB-A
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
1 PPON1
31 VSS
61 VDD15
91 CLKSEL
2 OCI20
32 AD23
62 AD12
92 HSMODE
3 VSS
33 AD22
63 AD11
93 TESTEN
4 PPON2
34 AD21
64 AD10
94 AVSS(R)
5 OCI30
35 AD20
65 VDD
95 RREF
6 PPON3
36 AD19
66 AD9
96 AVDD33
7 VDD
37 VDD
67 AD8
97 AVDD15
8 VCCRST0
38 AD18
68 CBE00
98 AVSS
9 PME0
39 VSS
69 N.C.
99 VSS
10 N.C.
40 AD17
70 AD7
100 VDD15
11 PCLK
41 AD16
71 VSS
101 DM1
12 VSS
42 CBE20
72 AD6
102 DP1
13 VBBRST0
43 FRAME0
73 AD5
103 VSS
14 INTA0
44 IRDY0
74 AD4
104 VSS
15 GNT0
45 VSS
75 VDD
105 DM2
16 REQ0
46 N.C.
76 AD3
106 DP2
17 AD31
47 TRDY0
77 AD2
107 VDD
18 VDD
19 AD30
48 VDD
49 DEVSEL0
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78
79
AD1
AD0
108 VDD
109 DM3
20 AD29
50 STOP0
80 VSS
110 DP3
21 VSS
51 PERR0
81 XT1/SCLK
111 VSS
22 AD28
52 SERR0
82 N.C.
112 VDD
23 AD27
53 PAR
83 XT2
113 N.C.
24 AD26
54 VSS
84 VDD
114 VSS
25 AD25
55 CBE10
85 CRUN0
115 VDD15OUT
26 AD24
56 AD15
86 SMI0
116 VDD
27 VDD
57 VDD
87 VSS
117 VDD
28 CBE30
58 AD14
88 SRCLK
118 TEST4
29 IDSEL
59 AD13
89 SRMOD
119 TEST3
30 VDD15
60 VSS
90 SRDTA
120 OCI10
Remark AVSS(R) should be used to connect RREF through 1 % precision reference resistor of 1.6 kΩ.
Data Sheet S17998EJ4V0DS
5
Datasheet pdf - http://www.DataSheet4U.co.kr/
5 Page 
2.3 Internal Regulator Circuit Connection
Figure 2–2. Internal Regulator Circuit Connection
μ
DD15
DD15
DD15
3.3 μ F (Ceramic type only)
μPD720102
Caution VDD15OUT must be routed to only VDD15 (and AVDD15). In case that VDD15OUT is also used for
power supply of other ICs, this may cause unstable operation of the μPD720102.
Remark VDD15 is powered by VDD15OUT from internal regulator. It is not necessary to use external regulator for
VDD15.
2.4 Analog Circuit Connection
Figure 2–3. Analog Circuit Connection
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μ
1.6 kΩ+−1 %
55
55
<R> Remark The board layout should minimize the total path length from RREF through the resistor to AVSS(R) and
path length to AVSS (analog ground). AVSS must be stable.
Data Sheet S17998EJ4V0DS
11
Datasheet pdf - http://www.DataSheet4U.co.kr/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD720102.PDF ] | |
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