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PDF M38503M2H-XXXFP Data sheet ( Hoja de datos )

Número de pieza M38503M2H-XXXFP
Descripción 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
Fabricantes Renesas 
Logotipo Renesas Logotipo



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No Preview Available ! M38503M2H-XXXFP Hoja de datos, Descripción, Manual

REJ09B0080-0103Z
8 3850 Group (Spec. H)
User's Manual
RENESAS 8-BIT CISC SINGLE-CHIP MICROCOMPUTER
740 FAMILY / 38000 SERIES
www.DataSheet.net/
Before using this material, please visit our website to confirm that this is the most
current document available.
Rev. 1.03
Revision date: Sep. 18, 2003
www.renesas.com
Datasheet pdf - http://www.DataSheet4U.co.kr/

1 page




M38503M2H-XXXFP pdf
Preface
This user’s manual describes Renesas’s CMOS 8-bit
microcomputers 3850 Group (Spec. H).
After reading this manual, the user should have a
through knowledge of the functions and features of
the 3850 Group (Spec. H), and should be able to
fully utilize the product. The manual starts with
specifications and ends with application examples.
For details of software, refer to the “740 Family
Software Manual”.
The user who is using the 3850 Group (standard)
needs to refer to not this manual but “3850/3851 Group
User’s Manual”.
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Datasheet pdf - http://www.DataSheet4U.co.kr/

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M38503M2H-XXXFP arduino
List of figures
Fig. 46 CPU rewrite mode set/reset flowchart ......................................................................... 1-42
Fig. 47 Program flowchart ........................................................................................................... 1-44
Fig. 48 Erase flowchart ............................................................................................................... 1-44
Fig. 49 Full status check flowchart and remedial procedure for errors ............................... 1-46
Fig. 50 ROM code protect control address .............................................................................. 1-47
Fig. 51 ID code store addresses ............................................................................................... 1-48
Fig. 52 Pin connection diagram in parallel I/O mode ............................................................. 1-51
Fig. 53 Page program flowchart ................................................................................................. 1-53
Fig. 54 Block erase flowchart ..................................................................................................... 1-53
Fig. 55 Full status check flowchart and remedial procedure for errors ............................... 1-55
Fig. 56 Connection for serial I/O mode .................................................................................... 1-58
Fig. 57 Timing for page read ..................................................................................................... 1-60
Fig. 58 Timing for reading the status register ......................................................................... 1-60
Fig. 59 Timing for clearing the status register ........................................................................ 1-60
Fig. 60 Timing for the page program ........................................................................................ 1-61
Fig. 61 Timing for erasing all blocks ........................................................................................ 1-61
Fig. 62 Timing for download ....................................................................................................... 1-62
Fig. 63 Timing for version information output .......................................................................... 1-62
Fig. 64 Timing for the ID check ................................................................................................. 1-63
Fig. 65 ID code storage addresses ........................................................................................... 1-63
Fig. 66 Full status check flowchart and remedial procedure for errors ............................... 1-65
Fig. 67 Example circuit application for the standard serial I/O mode .................................. 1-65
Fig. 68 Vcc power up/power down timing ................................................................................ 1-69
Fig. 69 AC wave for read operation .......................................................................................... 1-70
Fig. 70 AC electrical characteristics test condition for read operation ................................ 1-70
Fig. 71 AC wave for program operation (WE control) ............................................................ 1-71
Fig. 72 AC wave for program operation (CE control) ............................................................. 1-71
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Fig. 73 AC wave for erase operation (WE control) ................................................................ 1-72
Fig. 74 AC wave for erase operation (CE control) ................................................................. 1-72
Fig. 75 Programming and testing of One Time PROM version ............................................ 1-74
Fig. 76 A-D conversion equivalent circuit ................................................................................. 1-76
Fig. 77 A-D conversion timing chart .......................................................................................... 1-76
CHAPTER 2 APPLICATION
Fig. 2.1.1 Memory map of I/O port relevant registers .............................................................. 2-2
Fig. 2.1.2 Structure of Port Pi (i = 0, 1, 2, 3, 4) ...................................................................... 2-2
Fig. 2.1.3 Structure of Port Pi direction register (i = 0, 1, 2, 3, 4) ....................................... 2-3
Fig. 2.2.1 Memory map of registers relevant to interrupt ........................................................ 2-6
Fig. 2.2.2 Structure of Interrupt edge selection register .......................................................... 2-7
Fig. 2.2.3 Structure of Interrupt request register 1 ................................................................... 2-8
Fig. 2.2.4 Structure of Interrupt request register 2 ................................................................... 2-8
Fig. 2.2.5 Structure of Interrupt control register 1 .................................................................... 2-9
Fig. 2.2.6 Structure of Interrupt control register 2 .................................................................... 2-9
Fig. 2.2.7 Interrupt operation diagram ....................................................................................... 2-11
Fig. 2.2.8 Changes of stack pointer and program counter upon acceptance of interrupt request
........................................................................................................................................................ 2-12
Fig. 2.2.9 Time up to execution of interrupt processing routine ........................................... 2-13
Fig. 2.2.10 Timing chart after acceptance of interrupt request ............................................. 2-13
Fig. 2.2.11 Interrupt control diagram ......................................................................................... 2-14
Fig. 2.2.12 Example of multiple interrupts ................................................................................ 2-16
Fig. 2.2.13 Sequence of changing relevant register ............................................................... 2-18
3850 Group (Spec. H) User’s Manual
v
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