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PDF RTL8196C-GR Data sheet ( Hoja de datos )

Número de pieza RTL8196C-GR
Descripción IEEE 802.11n AP/ROUTER Network Processor
Fabricantes Realtek 
Logotipo Realtek Logotipo



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No Preview Available ! RTL8196C-GR Hoja de datos, Descripción, Manual

ial fileesd toRTL8196C-GR
nfident uthorizIEEE 802.11n AP/ROUTER NETWORK
co a 51PROCESSOR WITH EEE
www.DataSheet.net/
ltek ument T&W 7:17:DATASHEET
a c 1(CONFIDENTIAL: Development Partners Only)
Re he do 7-02 Rev. 1.2
T 0 23 March 2010
- Track ID: JATR-2265-11
010Realtek Semiconductor Corp.
2No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
Datasheet pdf - http://www.DataSheet4U.co.kr/

1 page




RTL8196C-GR pdf
RTL8196C
Datasheet
List of Tables
TABLE 1. PIN DESCRIPTIONS ........................................................................................................................................................6
TABLE 2. RTL8196C CONFIGURATION UPON POWER ON STRAPPING .........................................................................................9
TABLE 3. SHARED I/O PIN MAPPING ..........................................................................................................................................10
sTABLE 4. MEMORY CONTROL REGISTER (MCR) (0XB800_1000) .............................................................................................13
TABLE 5. DRAM CONFIGURATION REGISTER (DCR) (0XB800_1004)......................................................................................14
eTABLE 6. DRAM TIMING REGISTER (DTR) (0XB800_1008).....................................................................................................15
lTABLE 7. NOR FLASH CONFIGURATION REGISTER (NFCR) (0XB800_1100)............................................................................16
TABLE 8. SPI FLASH CONFIGURATION REGISTER (SFCR) (0XB800_1200) ...............................................................................16
iTABLE 9. SPI FLASH CONFIGURATION REGISTER 2 (SPCR2) (0XB800_1204) ..........................................................................17
f oTABLE 10. SPI FLASH CONTROL AND STATUS REGISTER (SFCSR) (0XB800_1208) ..................................................................18
tTABLE 11. SPI FLASH DATA REGISTER (SFDR) (0XB800_120C)...............................................................................................18
TABLE 12. SPI FLASH DATA REGISTER 2 (SFDR2) (0XB800_1210)...........................................................................................19
lTABLE 13. GPIO REGISTER SET (0XB800_3500)........................................................................................................................20
a dTABLE 14. GPIO PORT A, B, C, D CONTROL REGISTER (PABCD_CNR) (0XB800_3500) .........................................................20
TABLE 15. GPIO PORT A, B, C, D DIRECTION REGISTER (PABCD_DIR) (0XB800_3508) ........................................................21
i eTABLE 16. PORT A, B, C, D DATA REGISTER (PABCD_DAT) (0XB800_350C).........................................................................21
t zTABLE 17. PORT A, B, C, D INTERRUPT STATUS REGISTER (PABCD_ISR) (0XB800_3510)......................................................21
n iTABLE 18. PORT A, B INTERRUPT MASK REGISTER (PAB_IMR) (0XB800_3514) .....................................................................22
TABLE 19. PORT C, D INTERRUPT MASK REGISTER (PCD_IMR) (0XB800_3518) .....................................................................22
e rTABLE 20. SHARED PIN REGISTER (PIN_MUX_SEL) (0XB800_0040) ......................................................................................23
d oTABLE 21. SHARED PIN REGISTER (PIN_MUX_SEL2) (0XB800_003C)....................................................................................24
i hTABLE 22. OPERATING CONDITIONS ...........................................................................................................................................26
TABLE 23. POWER DISSIPATION ..................................................................................................................................................26
f tTABLE 24. SDRAM BUS DC PARAMETERS ................................................................................................................................27
n uTABLE 25. FLASH BUS DC PARAMETERS ....................................................................................................................................27
o a 1TABLE 26. USB 1.1 DC PARAMETERS.........................................................................................................................................28
c 5TABLE 27. USB 2.0 DC PARAMETERS.........................................................................................................................................28
TABLE 28. UART DC PARAMETERS ...........................................................................................................................................28
t :TABLE 29. GPIO DC PARAMETERS................................................w.ww.D.ataSh.eet.n.et/ .........................................................................................29
k n 7TABLE 30. JTAG DC PARAMETERS ............................................................................................................................................29
e e W 1TABLE 31. LED DC PARAMETERS ..............................................................................................................................................29
TABLE 32. CLOCK SIGNAL TIMING..............................................................................................................................................30
t m & :TABLE 33. SDRAM CLOCK TIMING............................................................................................................................................31
l u T 7TABLE 34. SDRAM INPUT TIMING .............................................................................................................................................32
TABLE 35. SDRAM OUTPUT TIMING..........................................................................................................................................32
a c 1TABLE 36. SDRAM ACCESS CONTROL TIMING ..........................................................................................................................33
TABLE 37. FLASH ACCESS TIMING VALUES ................................................................................................................................34
Re do 2TABLE 38. POWER-UP TIMING PARAMETERS ..............................................................................................................................34
TABLE 39. THERMAL OPERATING RANGE ...................................................................................................................................37
0TABLE 40. RTL8196C THERMAL PARAMETERS..........................................................................................................................37
The 2010-07-TABLE 41. ORDERING INFORMATION ..........................................................................................................................................39
IEEE 802.11n AP/Router Network Processor with EEE v
Track ID: JATR-2265-11 Rev. 1.2
Datasheet pdf - http://www.DataSheet4U.co.kr/

5 Page





RTL8196C-GR arduino
RTL8196C
Datasheet
4. Pin Assignments
4.1. Pin Assignments files toVDD10
LED_PORT2/GPIOB4
lLED_PORT3/GPIOB5
VDD33
a dLED_PORT4/GPIOB6
RESET#/GPIOB7
i eGPIOC[0]
VDD10_USB
t zGND
USB_DN
n iUSB_DP
AVDD33_USB_PCIE
e rHSON
HSOP
AVDD10_PCIE
d oREFCLKN
REFCLKP
i hAGND_PCIE
HSIN
f tHSIP
AVDD33_25M
n u40M_SEL
o a 140M_CLK
25M_XO
c 525M_XI
AVDD33_BG
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64 VDD33
63 MA14/BS1
62 MA10
61 MA0
60 MA1
59 MA2
58 MA3
57 MA12
56 MA11
55 MA9
54 VDD33
53 MA8
52 MA7
51 MA6
50 MA5
49 MA4
48 MA21/SF_SCK/GPIOC[5]
47 MA20/SF_SDIO0/GPIOC[4]
46 MA19/SF_SDIO1/GPIOC[3]
45 MA18/SF_SDIO2/GPIOC[2]
44 VDD33
43 MA17/SF_SDIO3/GPIOC[1]
42 GND
41 NF_CS0#/SF_CS0#
40 NF_CS1#/SF_CS1#/MCLKE/GPIOA1
39 VDD10
www.DataSheet.net/
altek cument T&W 17:17:Figure 2. Pin Assignments
R4e.2. PTachkeage Iddoentification 2010-07-02Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
IEEE 802.11n AP/Router Network Processor with EEE 5
Track ID: JATR-2265-11 Rev. 1.2
Datasheet pdf - http://www.DataSheet4U.co.kr/

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