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PDF GS8170LW36C Data sheet ( Hoja de datos )

Número de pieza GS8170LW36C
Descripción (GS8170LW36C / GS8170LW72C) Late Write SigmaRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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GS8170LW36/72C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
18Mb Σ1x1Lp CMOS I/O
Late Write SigmaRAM™
200 MHz–333 MHz
1.8 V VDD
1.8 V I/O
Features
• Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
Functional Description
SigmaRAM Family Overview
GS8170LW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
Bottom View
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Becausewww.DataSheet.co.kr SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Parameter Synopsis
Key Fast Bin Specs
Symbol
Cycle Time
tKHKH
Access Time
tKHQV
- 333
3.0 ns
1.6 ns
Rev: 2.03 1/2005
1/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/

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GS8170LW36C pdf
GS8170LW36/72C-333/300/250/200
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins
Single Data Rate (SDR) Pipelined Read.
Read A
Deselect
Read B
Read C
Read D
CK
Address
ADV
E1
W
DQ
CQ
A
B
Q(A)
CDE
Q(B)
Q(C)
Q(D)
Write Operations
www.DataSheet.co.kr
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Late Write
In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late
Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT
SRAMs
SigmaRAM Late Write with Pipelined Read
Read A
Deselect
Write B
Read C
Read D
CK
Address
ADV
E1
Bx
W
DQ
CQ
A
BCDE
Q(A)
D(B)
Q(C)
Q(D)
Rev: 2.03 1/2005
5/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/

5 Page





GS8170LW36C arduino
GS8170LW36/72C-333/300/250/200
CMOS I/O SigmaRAMs are supplied with selectable (high or low) impedance output drivers. The ZQ pin allows selection between
SRAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive strength (ZQ high) point-to-point
applications.
Late Write, Pipelined Read Truth Table
CK
E1
(tn)
E
(tn)
ADV
(tn)
W
(tn)
B
(tn)
Previous
Operation
Current Operation
DQ/CQ
(tn)
DQ/CQ
(tn+1)
01 X F 0 X X
X
Bank Deselect
***/***
Hi-Z/Hi-Z
01 X X 1 X X Bank Deselect
Bank Deselect (Continue)
Hi-Z/Hi-Z
Hi-Z/Hi-Z
01 1 T 0 X X
X
Deselect
***/***
Hi-Z/CQ
01 X X 1 X X
Deselect
Deselect (Continue)
Hi-Z/CQ
Hi-Z/CQ
01 0 T 0 0 T
X
Write
Loads new address
Stores DQx if Bx = 0
***/***
D1/CQ
01 0 T 0 0 F
X
Write (Abort)
Loads new address
No data stored
***/***
Hi-Z/CQ
01 X X 1 X T
Write
Write Continue
Increments address by 1
Stores DQx if Bx = 0
Dn-1/CQ
Dn/CQ
01 X X 1 X F
Write
Write Continue (Abort)www.DataSheet.co.kr
Increments address by 1
No data stored
Dn-1/CQ
Hi-Z/CQ
01 0 T 0 1 X
X
Read
Loads new address
***/***
Q1/CQ
01 X X 1 X X
Read
Read Continue
Increments address by 1
Qn-1/CQ
Qn/CQ
Notes:
1. If E2 = EP2 and E3 = EP3, then E = “T” else E = “F”.
2. If one or more Bx = 0, then B = “T” else B = “F”.
3. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
4. “***” indicates that the DQ input requirement / output state and CQ output state are determined by the previous operation.
5. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled.
6. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled.
7. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct
pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the ini-
tial external (base) address.
Rev: 2.03 1/2005
11/27
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2002, GSI Technology, Inc.
Datasheet pdf - http://www.DataSheet4U.net/

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