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PDF GS8170DW36C-300 Data sheet ( Hoja de datos )

Número de pieza GS8170DW36C-300
Descripción (GS8170DW36C / GS8170DW72C) Double Late Write SigmaRAM
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



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No Preview Available ! GS8170DW36C-300 Hoja de datos, Descripción, Manual

Preliminary
GS8170DW36/72C-333/300/250/200
209-Bump BGA
Commercial Temp
Industrial Temp
Σ18Mb
1x1Dp CMOS I/O
200 MHz–333 MHz
1.8 V VDD
Double Late Write SigmaRAM™
1.8 V I/O
Features
• Double Late Write mode, Pipelined Read mode
• JEDEC-standard SigmaRAMpinout and package
• 1.8 V +150/–100 mV core power supply
• 1.8 V CMOS Interface
• ZQ controlled user-selectable output drive strength
• Dual Cycle Deselect
• Burst Read and Write option
• Fully coherent read and write pipelines
• Echo Clock outputs track data output drivers
• Byte write operation (9-bit bytes)
• 2 user-programmable chip enable inputs
• IEEE 1149.1 JTAG-compliant Serial Boundary Scan
• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb
devices
Bottom View
Key Fast Bin Specs
Cycle Time
Symbol
tKHKH
- 333
3.0 ns
209-Bump, 14 mm x 22 mm BGA
1 mm Bump Pitch, 11 x 19 Bump Array
Access Time
tKHQV
1.6 ns
Functional Description
www.DataSheet.co.kr
SigmaRAM Family Overview
GS8170DW36/72 SigmaRAMs are built in compliance with
the SigmaRAM pinout standard for synchronous SRAMs.
They are 18,874,368-bit (18Mb) SRAMs. This family of wide,
very low voltage CMOS I/O SRAMs is designed to operate at
the speeds needed to implement economical high performance
networking systems.
Because SigmaRAMs are synchronous devices, address data
inputs and read/write control inputs are captured on the rising
edge of the input clock. Write cycles are internally self-timed
and initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation required by
asynchronous SRAMs and simplifies input signal timing.
ΣRAMs support pipelined reads utilizing a rising-edge-
triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
ΣRAMs are offered in a number of configurations including
Late Write, Double Late Write, and Double Data Rate (DDR).
The logical differences between the protocols employed by
these RAMs mainly involve various approaches to write
cueing and data transfer rates. The ΣRAMfamily standard
allows a user to implement the interface protocol best suited to
the task at hand.
ΣRAMs are implemented with high performance CMOS
technology and are packaged in a 209-bump BGA.
Rev: 2.01 5/2003
1/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/

1 page




GS8170DW36C-300 pdf
Preliminary
GS8170DW36/72C-333/300/250/200
Read Operations
Pipelined Read
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2,
and E3) are active, the write enable input signal (W) is deasserted high, and ADV is asserted low. The address presented to the
address inputs is latched into the address register and presented to the memory core and control logic. The control logic determines
that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge
of clock the read data is allowed to propagate through the output register and onto the output pins.
Single Data Rate Pipelined Read
Read
Deselect
Read
Read
Read
CK
Address
A
XX
C
D
E
F
ADV
/E1
/W
DQ
CQ
QA
www.DataSheet.co.kr
Key
Hi-Z
QC
Access
QD
Write Operations
Write operation occurs when the following conditions are satisfied at the rising edge of clock: All three chip enables (E1, E2, and
E3) are active, the write enable input signal (W) is asserted low, and ADV is asserted low.
Rev: 2.01 5/2003
5/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/

5 Page





GS8170DW36C-300 arduino
Preliminary
GS8170DW36/72C-333/300/250/200
Echo Clock Control in Two Banks of SigmaRAMs
Read
Read
Read
Read
Read
CK
Address
A
B
C
D
E
ADV
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
CQ
Bank 1
QA QC
F
CQ1 + CQ2
CQ
Bank 2
www.DataSheet.co.kr
DQ
Bank 2
QB
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Rev: 2.01 5/2003
11/30
© 2002, GSI Technology, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Datasheet pdf - http://www.DataSheet4U.net/

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