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Número de pieza | XC5VLX20T | |
Descripción | Fpga Integrated Circuit | |
Fabricantes | Xilinx | |
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Virtex-5 Family Overview
DS100 (v5.0) February 6, 2009
00
Product Specification
General Description
The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced
Silicon Modular Block) column-based architecture, the Virtex-5 family contains five distinct platforms (sub-families), the most choice
offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic
designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,
including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-
controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles
with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity,
PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance
PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of
performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5
FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength
of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP
designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and
connectivity capabilities. The Virtex-5 LXT, SXT, TXT, and FXT platforms include advanced high-speed serial connectivity and
link/transaction layer capability.
Summary of Virtex-5 FPGA Features
• Five platforms LX, LXT, SXT, TXT, and FXT
− Virtex-5 LX: High-performance general logic applications
− Virtex-5 LXT: High-performance logic with advanced serial
connectivity
− Virtex-5 SXT: High-performance signal processing
applications with advanced serial connectivity
− Virtex-5 TXT: High-performance systems with double
density advanced serial connectivity
− Virtex-5 FXT: High-performance embedded systems with
advanced serial connectivity
• Cross-platform compatibility
− LXT, SXT, and FXT devices are footprint compatible in the
same package using adjustable voltage regulators
• Most advanced, high-performance, optimal-utilization,
FPGA fabric
− Real 6-input look-up table (LUT) technology
− Dual 5-LUT option
− Improved reduced-hop routing
− 64-bit distributed RAM option
− SRL32/Dual SRL16 option
• Powerful clock management tile (CMT) clocking
− Digital Clock Manager (DCM) blocks for zero delay
buffering, frequency synthesis, and clock phase shifting
− PLL blocks for input jitter filtering, zero delay buffering,
frequency synthesis, and phase-matched clock division
• 36-Kbit block RAM/FIFOs
− True dual-port RAM blocks
− Enhanced optional programmable FIFO logic
− Programmable
- True dual-port widths up to x36
- Simple dual-port widths up to x72
− Built-in optional error-correction circuitry
− Optionally program each block as two independent 18-Kbit
blocks
• High-performance parallel SelectIO technology
− 1.2 to 3.3V I/O Operation
− Source-synchronous interfacing using ChipSync™
technology
− Digitally-controlled impedance (DCI) active termination
− Flexible fine-grained I/O banking
− High-speed memory interface support
• Advanced DSP48E slices
− 25 x 18, two’s complement, multiplication
− Optional adder, subtracter, and accumulator
− Optional pipelining
− Optional bitwise logical functionality
− Dedicated cascade connections
• Flexible configuration options
− SPI and Parallel FLASH interface
− Multi-bitstream support with dedicated fallback
reconfiguration logic
− Auto bus width detection capability
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• System Monitoring capability on all devices
− On-chip/Off-chip thermal monitoring
− On-chip/Off-chip power supply monitoring
− JTAG access to all monitored quantities
• Integrated Endpoint blocks for PCI Express Designs
− LXT, SXT, TXT, and FXT Platforms
− Compliant with the PCI Express Base Specification 1.1
− x1, x4, or x8 lane support per block
− Works in conjunction with RocketIO™ transceivers
• Tri-mode 10/100/1000 Mb/s Ethernet MACs
− LXT, SXT, TXT, and FXT Platforms
− RocketIO transceivers can be used as PHY or connect to
external PHY using many soft MII (Media Independent
Interface) options
• RocketIO GTP transceivers 100 Mb/s to 3.75 Gb/s
− LXT and SXT Platforms
• RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
− TXT and FXT Platforms
• PowerPC 440 Microprocessors
− FXT Platform only
− RISC architecture
− 7-stage pipeline
− 32-Kbyte instruction and data caches included
− Optimized processor interface structure (crossbar)
• 65-nm copper CMOS process technology
• 1.0V core voltage
• High signal-integrity flip-chip packaging available in standard
or Pb-free package options
© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PowerPC is a trademark of IBM Corp. and is used under license. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property
of their respective owners.
DS100 (v5.0) February 6, 2009
Product Specification
www.xilinx.com
1
Datasheet pdf - http://www.DataSheet4U.net/
1 page R Virtex-5 Family Overview
RocketIO GTP Transceivers (LXT/SXT only)
• Full-duplex serial transceiver capable of 100 Mb/s to
3.75 Gb/s baud rates
• 8B/10B, user-defined FPGA logic, or no encoding
options
• Channel bonding support
• CRC generation and checking
• Programmable pre-emphasis or pre-equalization for
the transmitter
• Programmable termination and voltage swing
• Programmable equalization for the receiver
• Receiver signal detect and loss of signal indicator
• User dynamic reconfiguration using secondary
configuration bus
• Out of Band (OOB) support for Serial ATA (SATA)
• Electrical idle, beaconing, receiver detection, and PCI
Express and SATA spread-spectrum clocking support
• Less than 100 mW typical power consumption
• Built-in PRBS Generators and Checkers
RocketIO GTX Transceivers (TXT/FXT only)
• Full-duplex serial transceiver capable of 150 Mb/s to
6.5 Gb/s baud rates
• 8B/10B encoding and programmable gearbox to
support 64B/66B and 64B/67B encoding, user-defined
FPGA logic, or no encoding options
• Channel bonding support
• CRC generation and checking
• Programmable pre-emphasis or pre-equalization for
the transmitter
• Programmable termination and voltage swing
• Programmable continuous time equalization for the
receiver
• Programmable decision feedback equalization for the
receiver
• Receiver signal detect and loss of signal indicator
• User dynamic reconfiguration using secondary
configuration bus
• OOB support (SATA)
• Electrical idle, beaconing, receiver detection, and
PCI Express spread-spectrum clocking support
• Low-power operation at all line rates
PowerPC 440 RISC Cores (FXT only)
• Embedded PowerPC 440 (PPC440) cores
− Up to 550 MHz operation
− Greater than 1000 DMIPS per core
− Seven-stage pipeline
− Multiple instructions per cycle
− Out-of-order execution
− 32 Kbyte, 64-way set associative level 1 instruction
cache
− 32 Kbyte, 64-way set associative level 1 data cache
− Book E compliant
• Integrated crossbar for enhanced system performance
− 128-bit Processor Local Buses (PLBs)
− Integrated scatter/gather DMA controllers
− Dedicated interface for connection to DDR2 memory
controller
− Auto-synchronization for non-integer PLB-to-CPU clock
ratios
• Auxiliary Processor Unit (APU) Interface and Controller
− Direct connection from PPC440 embedded block to
FPGA fabric-based coprocessors
− 128-bit wide pipelined APU Load/Store
− Support of autonomous instructions: no pipeline stalls
− Programmable decode for custom instructions
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DS100 (v5.0) February 6, 2009
Product Specification
www.xilinx.com
5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page R Virtex-5 Family Overview
Application Notes and Reference Designs
Application notes and reference designs written specifically for the Virtex-5 family are available on the Xilinx website at:
http://www.xilinx.com/virtex5
Virtex-5 Device and Package Combinations and Maximum I/Os
Table 2: Virtex-5 Device and Package Combinations and Maximum Available I/Os
Package
FF323
FFG323
FF324
FFG324
FF676 FF1153 FF1760
FFG676 FFG1153 FFG1760
FF665
FFG665
FF1136
FFG1136
FF1156
FFG1156
FF1738
FFG1738
FF1759
FFG1759
Size (mm) 19 x 19 19 x 19 27 x 27 35 x 35 42.5 x 42.5 27 x 27
35 x 35
35 x 35 42.5 x 42.5 42.5 x 42.5
Device
GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O GTs I/O
XC5VLX30
N/A 220 N/A 400
XC5VLX50
N/A 220 N/A 440 N/A 560
XC5VLX85
N/A 440 N/A 560
XC5VLX110
N/A 440 N/A 800 N/A 800
XC5VLX155
N/A 800 N/A 800
XC5VLX220
N/A 800
XC5VLX330
N/A 1,200
XC5VLX20T
4
GTPs
172
XC5VLX30T
4
GTPs
172
8
GTPs
360
XC5VLX50T
8
GTPs
360
12 GTPs
480
XC5VLX85T
12 GTPs 480
XC5VLX110T
16 GTPs 640
16 GTPs 680
XC5VLX155T
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16 GTPs 640
16 GTPs 680
XC5VLX220T
16 GTPs 680
XC5VLX330T
24 GTPs 960
XC5VSX35T
8
GTPs
360
XC5VSX50T
8
GTPs
360
12 GTPs
480
XC5VSX95T
16 GTPs 640
XC5VSX240T
24 GTPs 960
XC5VTX150T
40
GTXs
360
40
GTXs
680
XC5VTX240T
48
GTXs
680
XC5VFX30T
8
GTXs
360
XC5VFX70T
8
GTXs
360
16 GTXs
640
XC5VFX100T
16 GTXs 640
16 GTXs 680
XC5VFX130T
20 GTXs 840
XC5VFX200T
24 GTXs 960
Notes:
1. Flip-chip packages are also available in Pb-Free versions (FFG).
DS100 (v5.0) February 6, 2009
Product Specification
www.xilinx.com
11
Datasheet pdf - http://www.DataSheet4U.net/
11 Page |
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