PDF IDT82P5088 Data sheet ( Hoja de datos )

Número de pieza	IDT82P5088
Descripción	Universal Octal T1/E1/J1 LIU
Fabricantes	IDT
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Universal Octal T1/E1/J1 LIU with Inte- grated Clock Adapter IDT82P5088 FEATURES • Eight channel T1/E1/J1 long haul/short haul line interfaces • Supports HPS (Hitless Protection Switching) for 1+1 protection without external relays • Receiver sensitivity exceeds -36 dB@772KHz and -43 dB@1024 KHz • Programmable T1/E1/J1 switchability allowing one bill of ma- terial for any line condition • 3.3 V and 1.8 V power supply with 5 V tolerant inputs • Meets or exceeds specifications in - ANSI T1.102, T1.403 and T1.408 - ITU I.431, G.703,G.736, G.775 and G.823 - ETSI 300-166, 300-233 and TBR 12/13 - AT&T Pub 62411 • Per channel software selectable on: - Wave-shapingtemplatesforshorthaulandlonghaulLBO(LineBuild Out) - Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120 Ω) - Adjustment of arbitrary pulse shape - JA (Jitter Attenuator) position (receive path and transmit path) - Single rail/dual rail system interfaces - B8ZS/HDB3/AMI line encoding/decoding - Active edge of transmit clock (TCLK) and receive clock (RCLK) - Active level of transmit data (TDATA) and receive data (RDATA) - Receiver or transmitter power down - High impedance setting for line drivers - PRBS (Pseudo Random Bit Sequence) generation and detection with 215-1 PRBS polynomials for E1 - QRSS (Quasi Random Sequence Signals) generation and detection with 220-1 QRSS polynomials for T1/J1 - 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS error counter - Analog loopback, Digital loopback, Remote loopback and Inband loopback • Per channel cable attenuation indication • Adaptive receive sensitivity • Non-intrusive monitoring per ITU G.772 specification • Short circuit protection for line drivers • LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection • JTAG interface • Supports serial control interface, Motorola and Intel Non-Multi- plexed interfaces • Package: Available in 256-pin PBGA Green package options available www.DataSheet.co.kr DESCRIPTION The IDT82P5088 is an eight port line intereface that can be configured per port to any combination of T1, E1 or J1 ports. In receive path, an Adaptive Equalizer is integrated to remove the distortion introduced by the cable attenuation. The IDT82P5088 also performs clock/data recovery, AMI/ B8ZS/HDB3 line decoding and detects and reports the LOS conditions. In transmit path, there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper, LBOs and Jitter Attenuator for each channel. The Jitter Attenuators in trans- mit path and receive path both can be disabled. The IDT82P5088 supports both Single Rail and Dual Rail system interfaces. To facilitate the network maintenance, a PRBS/QRSS generation/detection circuit is integrated in each channel, and different types of loopbacks can be set on a per channel basis. Four different kinds of line terminating impedance, 75Ω, 100 Ω, 110 Ω and 120 Ω are selectable on a per channel basis. The chip also provides driver short-circuit protection and supports JTAG boundary scanning. The IDT82P5088 can be used in SDH/SONET, LAN, WAN, Routers, Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices, CSU/DSU equipment, etc. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.  2009 Integrated Device Technology, Inc. 1 February 5, 2009 DSC-7216/- Datasheet pdf - http://www.DataSheet4U.net/ 1 page IDT82P5088 UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 Absolute maximum Ratings .............................................................................................. 64 Recommended Operating Conditions ............................................................................... 64 D.C. Characteristics .......................................................................................................... 65 T1/J1 Line Receiver Electrical Characteristics ................................................................. 66 E1 Line Receiver Electrical Characteristics ...................................................................... 67 T1/J1 Line Transmitter Electrical Characteristics ............................................................. 67 E1 Line Transmitter Electrical Characteristics .................................................................. 68 Transmitter and Receiver Timing Characteristics ............................................................. 69 Jitter Tolerance ................................................................................................................. 70 6.9.1 T1/J1 Mode ............................................................................................................. 70 6.9.2 E1 Mode.................................................................................................................. 71 Jitter Transfer .................................................................................................................... 73 6.10.1 T1/J1 Mode ............................................................................................................. 73 6.10.2 E1 Mode.................................................................................................................. 74 7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 77 7.1 Motorola Non-Multiplexed Mode ....................................................................................... 77 7.1.1 Read Cycle Specification ........................................................................................ 77 7.1.2 Write Cycle Specification ........................................................................................ 77 7.2 Intel Non-Multiplexed Mode .............................................................................................. 78 7.2.1 Read Cycle Specification ........................................................................................ 78 7.2.2 Write Cycle Specification ........................................................................................ 79 7.3 SPI Mode .................................................ww.w.Data.Sheet.c.o.kr ...................................................................... 80 Tables of Contents 5 February 5, 2009 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page IDT82P5088 UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER Table-1 Pin Description (Continued) Name TD1/TDP1 TD2/TDP2 TD3/TDP3 TD4/TDP4 TD5/TDP5 TD6/TDP6 TD7/TDP7 TD8/TDP8 TDN1 TDN2 TDN3 TDN4 TDN5 TDN6 TDN7 TDN8 Type Input Pin No. PBGA256 G2 G4 F2 F4 E2 E4 D2 C2 G3 F1 F3 E1 E3 D1 C1 B1 Description Transmit and Receive Digital Data Interface TDn: Transmit Data for Channel 1~8 In Single Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDn is sampled into the device on the active edge of TCLKn. The active edge of TCLKn is selected by the TCLK_SEL bit (TCF0, 22H...). Data is encoded by AMI, HDB3 or B8ZS line code rules before being transmitted to the line. In this mode, TDNn should be connected to ground. TDPn/TDNn: Positive/Negative Transmit Data for Channel 1~8 In Dual Rail Mode, the NRZ data to be transmitted is input on these pins. Data on TDPn/TDNn is sampled into the device on the active edge of TCLKn. The active edge of the TCLKn is selected by the TCLK_SEL bit (TCF0, 22H...) The line code in Dual Rail Mode is as follows: TDPn 0 0 1 1 TDNn Output Pulse 0 Space 1 Positive Pulse 0 Negative Pulse 1 Space TCLK1 TCLK2 TCLK3 TCLK4 TCLK5 TCLK6 TCLK7 TCLK8 Input L3 TCLKn: Transmit Clock for Channel 1~8 L1 These pins input 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode transmit clock. The transmit data on TDn orT- K3 DPn/TDNn is sampled into the device on the active edge of TCLKn. If TCLKn is missing1 and the TCLKn missing inter- K1 rupt is not masked, an interrupt will be generated. J3 J1 H2 H4 RD1/RDP1 RD2/RDP2 RD3/RDP3 RD4/RDP4 RD5/RDP5 RD6/RDP6 RD7/RDP7 RD8/RDP8 Output P3 RDn: Receive Data for Channel 1~8www.DataSheet.co.kr R2 In Single Rail Mode, the NRZ receive data is output on these pins. Data is decoded according to AMI, HDB3 or B8ZS R1 line code rules. The active level on RDn pin is selected by the RD_INV bit (RCF0, 28H...). P1 N2 CVn: Code Violation for Channel 1~8 M4 In Single Rail Mode, the BPV/CV errors in received data streams will be reported by driving pin CVn to high level for M2 a full clock cycle. The B8ZS/HDB3 line code violation can be indicated when the B8ZS/HDB3 decoder is enabled. L5 When AMI decoder is selected, the bipolar violation can be indicated. CV1/RDN1 CV2/RDN2 CV3/RDN3 CV4/RDN4 CV5/RDN5 CV6/RDN6 CV7/RDN7 CV8/RDN8 T2 RDPn/RDNn: Positive/Negative Receive Data for Channel 1~8 T1 In Dual Rail Mode with Clock & Data Recovery (CDR), these pins output the NRZ data with the recovered clock. An P2 active level on RDPn indicates the receipt of a positive pulse on RTIPn/RRINGn while an active level on RDNn indi- N3 cates the receipt of a negative pulse on RTIPn/RRINGn. The active level on RDPn/RDNn is selected by the RD_INV N1 bit (RCF0, 28H...). When CDR is disabled, these pins directly output the raw RZ sliced data. The output data on RDn M3 and RDPn/RDNn is updated on the active edge of RCLKn. M1 L4 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 Output T6 RCLKn: Receive Clock for Channel 1~8 P6 These pins output 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions, if RAISE M6 bit (MAINT1, 2CH...) is ‘1’, RCLKn is derived from MCLK. R5 In clock recovery mode, these pins provide the clock recovered from the signal received on RTIPn/RRINGn. The N5 receive data (RDn in Single Rail Mode or RDPn/RDNn in Dual Rail Mode) is updated on the active edge of RCLKn. The T4 active edge is selected by the RCLK_SEL bit (RCF0, 28H...). P4 If clock recovery is bypassed, RCLKn is the exclusive OR(XOR) output of the Dual Rail sliced data RDPn and RDNn. T3 This signal can be used in the applications with external clock recovery circuitry. Notes: 1. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 clock cycles. PIN DESCRIPTION 11 February 5, 2009 Datasheet pdf - http://www.DataSheet4U.net/ 11 Page

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