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PDF IR2114SS Data sheet ( Hoja de datos )

Número de pieza IR2114SS
Descripción (IR2114SS - IR22141SS) HALF-BRIDGE GATE DRIVER IC
Fabricantes International Rectifier 
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No Preview Available ! IR2114SS Hoja de datos, Descripción, Manual

Data Sheet No. PD60213 revC
IR2114SS/ IR21141SS
IR2214SS/IR22141SS
HALF-BRIDGE GATE DRIVER IC
Features
Floating channel up to +600 or +1200V
Soft over-current shutdown
Synchronization signal to synchronize shut down with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched delay outputs
Under voltage lockout with hysteresis band
Description
The IR2114/21141/2214/IR22141 gate driver family is suited to drive a single
half bridge in power switching applications. The high gate driving capability (2A
source, 3A sink) and the low quiescent current enable bootstrap supply
techniques in medium power systems. These drivers feature full short circuit
protection by means of the power transistor desaturation detection and manages
all the half-bridge faults by turning off smoothly the desaturated transistor
through the dedicated soft shut down pin, therefore preventing over-voltages and
reducing EM emissions. In multi-phase system IR2114/21141/2214/IR22141
drivers communicate using a dedicated local network (SY_FLT and FAULT/SD
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signals) to properly manage phase-to-phase short circuits. The system controller
may force shutdown or read device fault state through the 3.3 V compatible
CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise,
the control and power ground use dedicated pins enabling low-side emitter
current sensing as well. Undervoltage conditions in floating and low voltage
circuits are managed independently.
Product Summary
VOFFSET
IO+/- (typ)
VOUT
Deadtime matching (max)
Deadtime (typ)
Desat blanking time (typ)
DSH, DSL input voltage
threshold (typ)
Soft shutdown time (typ)
600V or
1200V max.
2.0 A / 3.0A
10.4V - 20V
75 nsec
330 nsec
3 µsec
8.0 V
9.25 µsec
Package
24-Lead SSOP
Typical connection
DC+
15 V
DC BUS uP,
(1200V) Control
VCC
LIN
HIN
FAULT/SD
FLT_CLR
SY_FLT
VSS
VB
HOP
HON
SSDH
DSH
VS
LOP
LON
SSDL
DSL
COM
Motor
DC-
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IR2114SS pdf
IR2114/IR21141/IR2214/IR22141
Pin: HOP, LOP
Symbol
Definition
VOH
High level output voltage, VB – VHOP or Vcc –VLOP
IO1+ Output high first stage short circuit pulsed current
IO2+ Output high second stage short circuit pulsed current
Min Typ Max Units Test Conditions
- 40 300 mV
IO = 20mA
-2 -
VHOP/LOP=0V,
HIN or LIN= 1,
PW200ns,
resistive load,
see Fig. 8
- 1 - A VHOP/LOP=0V,
HIN or LIN = 1,
400nsPW10µs,
resistive load,
see Fig. 8
on/off
internal signal
200ns
oneshot
VCC/VB
VOH
LOP/HOP
Figure 5: HOP and LOP diagram
Pin: HON, LON, SSDH, SSDL
Symbol
Definition
VOL
RON,SSD
IO-
Low level output voltage, VHON or VLON
Soft Shutdown on resistance (Note 1)
Output low short circuit pulsed current
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Note 1: SSD operation only.
Min Typ Max Units Test Conditions
- 45 300 mV IO = 20mA
- 90 -
PW 7 µs
- 3 - A VHOP/LOP=15V,
HIN or LIN = 0,
PW10µs
LON/HON
on/off
internal signal
desat
internal signal
RON,SSD
SSDL/SSDH
VOL
COM/VS
Figure 6: HON, LON, SSDH and SSDL diagram
5
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IR2114SS arduino
IR2114/IR21141/IR2214/IR22141
Logic Table
Output drivers status description
HO/LO HOP/LOP HON/LON SSDH/SSDL
status
0 HiZ 0
HiZ
1 1 HiZ HiZ
SSD
HiZ
HiZ
0
LO/HO
Output follows inputs (in=1->out=1, in=0->out=0)
LOn-1/HOn-1
Output keeps previous status
INPUTS
INPUT/OUTPUT
Under Voltage
Yes: V< UV threshold
No : V> UV threshold
X : don’t care
OUTPUTS
SY_FLT
FAULT/SD
VCC VBS HO LO
Operation Hin Lin FLT_CLR SSD: desat (out)
SD: shutdown (in)
HOLD: freezing (in) FAULT: diagnostic (out)
Shut Down X X
X
X
0 (SD)
XX00
Fault Clear HIN LIN
NOTE1
(FAULT)
No No HO LO
10
0
1
1
No No
1
0
Normal
01
Operation 0 0
Anti Shoot
Through
1
1
Soft Shut 1 0
Down
(entering) 0 1
Soft Shut X X
Down
(finishing) X X
0
0
0
0
0
0
0
1
1
1
(SSD)
(SSD)
(SSD)
(SSD)
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1
1
1
1
1
(FAULT)
(FAULT)
No No
0
1
No No
0
0
No No
0
0
No No SSD 0
No No
0 SSD
No No
0
0
No No
0
0
Freeze
XX
X
0 (HOLD)
1 No No HOn-1 LOn-1
Under
Voltage
X LIN
XX
X
X
1
1
1
0 (FAULT)
No Yes 0 LO
Yes X 0 0
NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required. In order to avoid
FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active.
11
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