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PDF NJU26060 Data sheet ( Hoja de datos )

Número de pieza NJU26060
Descripción 24bit Fixed-point Digital Signal Processing
Fabricantes New Japan Radio 
Logotipo New Japan Radio Logotipo



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NJU26060 Series
NJU26060 Series Hardware Specification
General Description
The NJU26060 Series is a high performance 24-bit digital signal
processor. The NJU26060 Series provides stereo PWM modulators, one
Sampling Rate Convertor(SRC), Digital Interface Transemitor(DIT) and
four GPI/O ports.
The NJU26060 Series with the OTP(One Time Programmable) function
provides the wide range of applications of sound technologies and fast time
to market service.
Package
NJU26060V
Features
- Hardware
24bit Fixed-point Digital Signal Processing
Maximum Clock Frequency
: 24.576MHz (Standard), Embedded PLL Circuit
PWM modulator
: stereo 4ch Outputs
Sampling rate converter (SRC) : Fs=8kHz 192kHz 48kHz
Digital interface transmitter (DIT)
Digital Audio Interface
Digital Audio Format
: 3 Input ports / 3 Output ports
: I2S 24bit, Left-justified, Right-justified, BCK : 32/64fs
Master / Slave Mode
- Sampling Rate Converter: Slave mode
- In Master Mode: MCKO(256 or 512fs ), BCKO(64 or 32fs ), BCK (1fs )
Host Interface
- I2C Bus ( Fast-mode/400kbps)
Power Supply
: VDD = 3.3V
Input terminal:
: 5V Input tolerant
Package
: SSOP44 (Pb-Free)
Ver.2010-07-21
-1-
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NJU26060 pdf
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NJU26060 Series
Absolute Maximum Ratings
Table2 Absolute Maximum Ratings
Parameter
Symbol
Supply Voltage *
Supply Voltage Bypass *
Supply Voltage PLL *
In
VDD, VDDPWM
VREGO
VDDPLL
Vx(IN)
I/O, O/D
Vx(I/O), Vx(OD)
Terminal Voltage * Out
Vx(OUT)
CLK
Vx(CLK)
CLKOUT
Vx(CLKOUT)
Power Dissipation
PD
Operating Temperature
Storage Temperature
TOPR
TSTR
( VSS=VSSPLL=VSSIO=0V, Ta=25°C )
Rating
Units
-0.3 to 4.2
-0.3 to 2.3
V
-0.3 to 2.3
-0.3 to 5.5 (VDDIO3.0V)
-0.3 to 4.2 (VDDIO<3.0V)
-0.3 to 4.2
V
-0.3 to 4.2
-0.3 to 4.2
800
It mounts on the board of the EIAJ spec.
76.2 x 114.3 x 1.6mm, 2layer, FR-4
-40 to 85
-40 to 125
mW
°C
°C
* VDD
* VDDPW
* VREGO
* VDDPLL
* Vx(IN)
* Vx(OD)
* Vx(I/O)
* Vx(OUT)
* Vx(CLK)
* Vx(CLKOUT)
: 12, 33 pin
: 23 pin
: 14, 31 pin
: 15 pin
: 1~3, 5~11, 29, 30, 36 pin
: 4 pin
: 37~40 pin
: 17~21, 24~28, 41~44 pin
: 35 pin
: 34 pin
Equivalent Circuits
RPU
PAD
RPD
VDD
VREGO
CLK
VSS
CLKOUT
Input Pin, I/O Pin (Input port)
PAD
VDD or VDDPWM
Output
VSS or VSSPWM
VSSIO
Output Pin, I/O Pin (Output port)
(4pin Open-Drain Out)
PAD
CLK/CLKOUT Pin
REGDISb Pin
Fig.3 NJU26060 Series Equivalent Circuits
VDD
VREGO
VSS
VDD
VSS
Ver.2010-07-21
-5-
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NJU26060 Series
3.2 Sampling Frequency Conversion Ratio and Group Delay
After the automatic detection reset or the firmware reset is done, the SRC generates an effective
conversion output within 256 input samples. The NJU26060 Series does not generate digital noise after
this kind of reset. The conversion ratio comes to the target specification and fixes conversion ratio within
16,384 input samples after the reset. After the automatic detection reset or the firmware reset, the LRI
clock should be stable.
In case of the sampling converter ratio is fixed, the group delay is 256 sampling frequency clocks. To
transfer the data to the firmware, it takes five more sampling frequency clocks. The zero data is inputted
into the SRC during the group delay period, the output data of the SRC becomes zero.
3.3 Jitter-Tolerated Dose
The SRC can accept the jitter of 0.1UI. The UI is abbreviation of unit interval. The 1UI is one LRI clock
time. The UI is defined by single peak.
Ex.1) Fs=8kHz 0.1UI = 0.1/8,000=12.5µsec
Ex.2) Fs=192kHz 0.1UI = 0.1/192,000=521nsec
The jitter-tolerated dose is shown in fig.7. The dotted line (0.1UI) is acceptable limitation to keep the
performance of the SRC. The lack of data occurs above the solid line. Above the solid line, audible noise
is generated.
This characteristic is measured with the sine wave jitter. Also the SRC can convert the square wave
with the jitter very well as far as lower than 0.1U area.
Some kind of product generates high peak jitter instantaneously. For example, some kind of USB audio
product. When the signal with more than 0.1U jitter is connected to the SRC, the SRC has possibility to
generate audible noise.
10
Area where data is missed
1 and noise is generated
Deteriorates area
0.1
Excellent characteristic area
0.01
1
Ver.2010-07-21
10 100 1000
Jitter Frequency [Hz]
Fig.7 Jitter Tolerated dose
10000
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