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PDF W9864G2GH Data sheet ( Hoja de datos )

Número de pieza W9864G2GH
Descripción 512K X 4 BANKS X 32BITS SDRAM
Fabricantes Winbond 
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No Preview Available ! W9864G2GH Hoja de datos, Descripción, Manual

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W9864G2GH
512K X 4 BANKS X 32BITS SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER...................................................................................................... 4
4. PIN CONFIGURATION ............................................................................................................... 5
5. PIN DESCRIPTION..................................................................................................................... 6
6. BLOCK DIAGRAM ...................................................................................................................... 7
7. FUNCTIONAL DESCRIPTION.................................................................................................... 8
7.1 Power Up and Initialization ............................................................................................. 8
7.2 Programming Mode Register.......................................................................................... 8
7.3 Bank Activate Command ................................................................................................ 8
7.4 Read and Write Access Modes ...................................................................................... 8
7.5 Burst Read Command .................................................................................................... 9
7.6 Burst Command .............................................................................................................. 9
7.7 Read Interrupted by a Read ........................................................................................... 9
7.8 Read Interrupted by a Write............................................................................................ 9
7.9 Write Interrupted by a Write............................................................................................ 9
7.10 Write Interrupted by a Read............................................................................................ 9
7.11 Burst Stop Command ................................................................................................... 10
7.12 Addressing Sequence of Sequential Mode .................................................................. 10
7.13 Addressing Sequence of Interleave Mode.................................................................... 10
7.14 Auto-precharge Command ........................................................................................... 11
7.15 Precharge Command.................................................................................................... 11
7.16 Self Refresh Command ................................................................................................ 11
7.17 Power Down Mode ....................................................................................................... 12
7.18 No Operation Command............................................................................................... 12
7.19 Deselect Command ...................................................................................................... 12
7.20 Clock Suspend Mode.................................................................................................... 12
8. OPERATION MODE ................................................................................................................. 13
8.1 Simplified Stated Diagram ............................................................................................ 14
9. ELECTRICAL CHARACTERISTICS......................................................................................... 15
9.1 Absolute Maximum Ratings .......................................................................................... 15
Publication Release Date:Aug. 13, 2007
- 1 - Revision A09
Datasheet pdf - http://www.DataSheet4U.net/

1 page




W9864G2GH pdf
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4. PIN CONFIGURATION
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
NC
VCC
DQM0
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
DQM2
VCC
NC
DQ16
VSSQ
DQ17
DQ18
VCCQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VCCQ
DQ23
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
W9864G2GH
86 Vss
85 DQ15
84 VSSQ
83 DQ14
82 DQ13
81 VCCQ
80 DQ12
79 DQ11
78 VSSQ
77 DQ10
76 DQ9
75 VCCQ
74 DQ8
73 NC
72 VSS
71 DQM1
70 NC
69 NC
68 CLK
67 CKE
66 A9
65 A8
64 A7
63 A6
62 A5
61 A4
60 A3
59 DQM3
58 VSS
57 NC
56 DQ31
55 VCCQ
54 DQ30
53 DQ29
52 VSSQ
51 DQ28
50 DQ27
49 VCCQ
48 DQ26
47 DQ25
46 VSSQ
45 DQ24
44 VSS
-5-
Publication Release Date:Aug. 13, 2007
Revision A09
Datasheet pdf - http://www.DataSheet4U.net/

5 Page





W9864G2GH arduino
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W9864G2GH
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with Auto-precharge cannot be interrupted before the entire burst
operation is completed for the same bank. Therefore, use of a Read, Write, or Precharge Command is
prohibited during a read or write cycle with Auto-precharge. Once the precharge operation has started,
the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-
precharge command is illegal if the burst is set to full page length. If A10 is high when a Write
Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically
enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred
to as write tWR. The bank undergoing Auto-precharge cannot be reactivated until tWR and tRP are
satisfied. This is referred to as tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-
precharge Command, the interval between the Bank Activate Command and the beginning of the
internal precharge operation must satisfy tRAS (min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. Three address bits, A10, BS0 and BS1 are used to define which bank(s) is to
be precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will
exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal
to the tAC cycle time plus the Self Refresh exit time.
If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and
just after exiting the self refresh mode.
- 11 -
Publication Release Date:Aug. 13, 2007
Revision A09
Datasheet pdf - http://www.DataSheet4U.net/

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