|
|
PDF W972GG8JB Data sheet ( Hoja de datos )
| Número de pieza | W972GG8JB | |
| Descripción | 32M X 8 BANKS X 8 BIT DDR2 SDRAM | |
| Fabricantes | Winbond | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de W972GG8JB (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet.co.kr
W972GG8JB
32M 8 BANKS 8 BIT DDR2 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................4
2. FEATURES ...........................................................................................................................................4
3. KEY PARAMETERS .............................................................................................................................5
4. BALL CONFIGURATION ......................................................................................................................6
5. BALL DESCRIPTION............................................................................................................................7
6. BLOCK DIAGRAM ................................................................................................................................8
7. FUNCTIONAL DESCRIPTION..............................................................................................................9
7.1 Power-up and Initialization Sequence ...................................................................................................9
7.2 Mode Register and Extended Mode Registers Operation ...................................................................10
7.2.1
Mode Register Set Command (MRS)...............................................................................10
7.2.2
Extend Mode Register Set Commands (EMRS) ..............................................................11
7.2.2.1
7.2.2.2
Extend Mode Register Set Command (1), EMR (1)................................................11
DLL Enable/Disable................................................................................................12
7.2.2.3
Extend Mode Register Set Command (2), EMR (2)................................................13
7.2.2.4
Extend Mode Register Set Command (3), EMR (3)................................................14
7.2.3
Off-Chip Driver (OCD) Impedance Adjustment ................................................................15
7.2.3.1
Extended Mode Register for OCD Impedance Adjustment ....................................16
7.2.3.2
7.2.3.3
OCD Impedance Adjust..........................................................................................16
Drive Mode .............................................................................................................17
7.2.4
On-Die Termination (ODT)...............................................................................................18
7.2.5
ODT related timings .........................................................................................................18
7.2.5.1
MRS command to ODT update delay.....................................................................18
7.3 Command Function.............................................................................................................................20
7.3.1
Bank Activate Command..................................................................................................20
7.3.2
Read Command ...............................................................................................................21
7.3.3
7.3.4
Write Command ...............................................................................................................21
Burst Read with Auto-precharge Command.....................................................................21
7.3.5
7.3.6
7.3.7
Burst Write with Auto-precharge Command.....................................................................21
Precharge All Command ..................................................................................................21
Self Refresh Entry Command ..........................................................................................21
7.3.8
Self Refresh Exit Command.............................................................................................22
7.3.9
7.3.10
Refresh Command ...........................................................................................................22
No-Operation Command ..................................................................................................23
7.3.11
Device Deselect Command..............................................................................................23
7.4 Read and Write access modes ...........................................................................................................23
7.4.1
Posted CAS ....................................................................................................................23
7.4.1.1
Examples of posted CAS operation .....................................................................23
Publication Release Date: Feb. 18, 2011
- 1 - Revision A02
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
W972GG8JB
3. KEY PARAMETERS
SYM.
SPEED GRADE
Bin(CL-tRCD-tRP)
Part Number Extension
@CL = 7
@CL = 6
tCK(avg) Average clock period
@CL = 5
@CL = 4
@CL = 3
tRCD
tRP
tRC
tRAS
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating one bank active-precharge current
Operating one bank active-read-precharge current
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (TCASE ≤ 85°C)
Operating bank interleave read current
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
DDR2-1066
7-7-7
-18
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
7.5 nS
3.75 nS
7.5 nS
13.125 nS
13.125 nS
58.125 nS
45 nS
85 mA
85 mA
165 mA
145 mA
175 mA
12 mA
220 mA
DDR2-800
5-5-5/6-6-6
-25/25I
2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
12.5 nS
57.5 nS
45 nS
72 mA
80 mA
135 mA
120 mA
160 mA
12 mA
200 mA
DDR2-667
5-5-5
-3
3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
15 nS
60 nS
45 nS
69 mA
75 mA
120 mA
110 mA
150 mA
12 mA
180 mA
-5-
Publication Release Date: Feb. 18, 2011
Revision A02
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
W972GG8JB
A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field
0 0 0 0 0 PD
WR
DLL TM CAS Latency BT Burst Length
Mode Register
A8 DLL Reset
0 No
1 Yes
A7 Mode
0 Normal
1 Test
BA1
0
0
1
1
BA0
0
1
0
1
A12
0
1
MRS mode
MR
Write recovery for Auto-precharge
EMR (1)
A11 A10 A9
WR *
EMR (2)
0 0 0 Reserved
EMR (3)
001
2
010
3
Active power down exit time
011
4
Fast exit (use tXARD)
100
5
Slow exit (use tXARDS)
101
6
110
7
111
8
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0
010
011
BL
4
8
CAS Latency
A6 A5 A4
000
001
010
011
100
101
110
111
Latency
Reserved
Reserved
Reserved
3
4
5
6
7
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
Figure 2 – Mode Register Set (MRS)
7.2.2 Extend Mode Register Set Commands (EMRS)
7.2.2.1 Extend Mode Register Set Command (1), EMR (1)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L, BA2 = "L" A0 to A14 =
Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used
for ODT setting.
- 11 -
Publication Release Date: Feb. 18, 2011
Revision A02
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet W972GG8JB.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| W972GG8JB | 32M X 8 BANKS X 8 BIT DDR2 SDRAM | Winbond |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |