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Número de pieza W971GG6JB
Descripción 8M X 8 BANKS X 16 BIT DDR2 SDRAM
Fabricantes Winbond 
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W971GG6JB
8M 8 BANKS 16 BIT DDR2 SDRAM
Table of Contents-
1. GENERAL DESCRIPTION ...................................................................................................................4
2. FEATURES ...........................................................................................................................................4
3. KEY PARAMETERS .............................................................................................................................5
4. BALL CONFIGURATION ......................................................................................................................6
5. BALL DESCRIPTION............................................................................................................................7
6. BLOCK DIAGRAM ................................................................................................................................8
7. FUNCTIONAL DESCRIPTION..............................................................................................................9
7.1 Power-up and Initialization Sequence ...................................................................................................9
7.2 Mode Register and Extended Mode Registers Operation ...................................................................10
7.2.1
Mode Register Set Command (MRS)...............................................................................10
7.2.2
Extend Mode Register Set Commands (EMRS) ..............................................................11
7.2.2.1
Extend Mode Register Set Command (1), EMR (1)................................................11
7.2.2.2
DLL Enable/Disable................................................................................................12
7.2.2.3
Extend Mode Register Set Command (2), EMR (2)................................................13
7.2.2.4
Extend Mode Register Set Command (3), EMR (3)................................................14
7.2.3
Off-Chip Driver (OCD) Impedance Adjustment ................................................................15
7.2.3.1
Extended Mode Register for OCD Impedance Adjustment ....................................16
7.2.3.2
OCD Impedance Adjust..........................................................................................16
7.2.3.3
Drive Mode .............................................................................................................17
7.2.4
On-Die Termination (ODT)...............................................................................................18
7.2.5
ODT related timings .........................................................................................................18
7.2.5.1
MRS command to ODT update delay.....................................................................18
7.3 Command Function.............................................................................................................................20
7.3.1
Bank Activate Command..................................................................................................20
7.3.2
Read Command ...............................................................................................................21
7.3.3
Write Command ...............................................................................................................21
7.3.4
Burst Read with Auto-precharge Command.....................................................................21
7.3.5
Burst Write with Auto-precharge Command.....................................................................21
7.3.6
Precharge All Command ..................................................................................................21
7.3.7
Self Refresh Entry Command ..........................................................................................21
7.3.8
Self Refresh Exit Command.............................................................................................22
7.3.9
Refresh Command ...........................................................................................................22
7.3.10
No-Operation Command ..................................................................................................23
7.3.11
Device Deselect Command..............................................................................................23
7.4 Read and Write access modes ...........................................................................................................23
7.4.1
Posted CAS ....................................................................................................................23
Publication Release Date: Nov. 18, 2011
- 1 - Revision A08
Datasheet pdf - http://www.DataSheet4U.net/

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W971GG6JB
3. KEY PARAMETERS
SPEED GRADE
DDR2-1066 DDR2-800 DDR2-800 DDR2-667
SYM.
Bin(CL-tRCD-tRP)
6-6-6
5-5-5
5-5-5
5-5-5
Part Number Extension
-18 -25/25I/25A/25K 25L
-3
@CL = 7
Min.
Max.
1.875 nS
7.5 nS


@CL = 6
Min.
Max.
1.875 nS
7.5 nS
2.5 nS
8 nS
2.5 nS
8 nS
tCK(avg) Average clock period
@CL = 5
Min.
Max.
2.5 nS
7.5 nS
2.5 nS
8 nS
2.5 nS
8 nS
3 nS
8 nS
@CL = 4
Min.
Max.
3 nS
7.5 nS
3.75 nS
8 nS
3.75 nS
8 nS
3.75 nS
8 nS
@CL = 3
Min.
Max.
5 nS
8 nS
5 nS
8 nS
5 nS
8 nS
tRCD
tREFI
Active to Read/Write Command Delay Time
-40°C TCASE 85°C
Average periodic
refresh Interval
0°C TCASE 85°C
85°C < TCASE 95°C
95°C < TCASE 105°C
Min.
Max.
11.25 nS
*2
7.8 μS*1
3.9 μS*4
*6
12.5 nS
7.8 μS*2, 3
7.8 μS*1
3.9 μS*4
3.9 μS*5
12.5 nS
*2
7.8 μS*1
3.9 μS*4
*6
15 nS
*2
7.8 μS*1
3.9 μS*4
*6
tRP Precharge to Active Command Period
Min. 11.25 nS
12.5 nS 12.5 nS
15 nS
tRC Active to Ref/Active Command Period
Min. 51.25 nS
52.5 nS 52.5 nS
55 nS
tRAS Active to Precharge Command Period
Min. 40 nS
40 nS
40 nS
40 nS
IDD0 Operating one bank active-precharge current
Max.
85 mA
80 mA 80 mA 75 mA
IDD1 Operating one bank active-read-precharge current Max.
90 mA
85 mA 85 mA 80 mA
IDD2P Precharge power-down current
Max.
10 mA
10 mA
7 mA 10 mA
IDD4R Operating burst read current
Max.
155 mA
130 mA 130 mA 120 mA
IDD4W Operating burst write current
Max.
160 mA
135 mA 135 mA 125 mA
IDD5B
IDD6
Burst refresh current
Self refresh current (TCASE 85C)
Max.
Max.
145 mA
10 mA
130 mA
10 mA
130 mA
4 mA
120 mA
10 mA
IDD7 Operating bank interleave read current
Max.
285 mA
225 mA 225 mA 195 mA
Notes:
1. All speed grades support 0°C TCASE 85°C with full JEDEC AC and DC specifications.
2. For -18, -25, 25L and -3 speed grades, -40°C TCASE < 0°C is not available.
3. 25I, 25A and 25K speed grades support -40°C TCASE 85°C with full JEDEC AC and DC specifications.
4. For all speed grade parts, TCASE is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( tREFI = 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 "1" on EMR (2).
5. For 25K automotive speed grade, TCASE is able to extend to 105°C with doubling Auto Refresh commands in frequency to a
32 mS period ( tREFI = 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 "1" on EMR (2).
6. For -18, -25, 25L, 25I, 25A and -3 speed grades, 95°C < TCASE ≤ 105°C is not available.
-5-
Publication Release Date: Nov. 18, 2011
Revision A08
Datasheet pdf - http://www.DataSheet4U.net/

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W971GG6JB
A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA2 BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Field
0 0 0 PD
WR
DLL TM CAS Latency BT Burst Length
Mode Register
A8 DLL Reset
0 No
1 Yes
BA1 BA0
00
01
10
11
MRS mode
MR
EMR (1)
EMR (2)
EMR (3)
A12 Active power down exit time
0 Fast exit (use tXARD)
1 Slow exit (use tXARDS)
A7 Mode
0 Normal
1 Test
Write recovery for Auto-precharge
A11 A10 A9
WR *
0 0 0 Reserved
001
2
010
3
011
4
100
5
101
6
110
7
111
8
A3 Burst Type
0 Sequential
1 Interleave
Burst Length
A2 A1 A0
010
011
BL
4
8
CAS Latency
A6 A5 A4 Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
011
3
100
4
101
110
111
5
6
7
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
Figure 2 Mode Register Set (MRS)
7.2.2 Extend Mode Register Set Commands (EMRS)
7.2.2.1 Extend Mode Register Set Command (1), EMR (1)
( CS = "L", RAS = "L", CAS = "L", WE = "L", BA0 = "H", BA1 = "L, BA2 = "L" A0 to A12 =
Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT, DQS disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for DQS disable. A2 and A6 are used
for ODT setting.
- 11 -
Publication Release Date: Nov. 18, 2011
Revision A08
Datasheet pdf - http://www.DataSheet4U.net/

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