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PDF W9412G6CH Data sheet ( Hoja de datos )

Número de pieza W9412G6CH
Descripción 2M X 4 BANKS X 16 BITS DDR SDRAM
Fabricantes Winbond 
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W9412G6CH
2M × 4 BANKS × 16 BITS DDR SDRAM
Table of Contents-
1. GENERAL DESCRIPTION .............................................................................................................. 4
2. FEATURES ...................................................................................................................................... 4
3. KEY PARAMETERS ........................................................................................................................ 5
4. PIN CONFIGURATION .................................................................................................................... 6
5. PIN DESCRIPTION.......................................................................................................................... 7
6. BLOCK DIAGRAM ........................................................................................................................... 8
7. FUNCTIONAL DESCRIPTION......................................................................................................... 9
7.1 Power Up Sequence ............................................................................................................. 9
7.2 Command Function ............................................................................................................... 9
7.2.1
7.2.2
7.2.3
Bank Activate Command ..................................................................................................9
Bank Precharge Command ..............................................................................................9
Precharge All Command ..................................................................................................9
7.2.4 Write Command................................................................................................................9
7.2.5 Write with Auto-precharge Command.............................................................................10
7.2.6 Read Command .............................................................................................................10
7.2.7 Read with Auto-precharge Command ............................................................................10
7.2.8 Mode Register Set Command ........................................................................................10
7.2.9 Extended Mode Register Set Command ........................................................................10
7.2.10 No-Operation Command ................................................................................................11
7.2.11 Burst Read Stop Command............................................................................................11
7.2.12 Device Deselect Command ............................................................................................11
7.2.13 Auto Refresh Command .................................................................................................11
7.2.14 Self Refresh Entry Command .........................................................................................11
7.2.15 Self Refresh Exit Command ...........................................................................................12
7.2.16 Data Write Enable /Disable Command ...........................................................................12
7.3 Read Operation ................................................................................................................... 12
7.4 Write Operation ................................................................................................................... 12
7.5 Precharge ............................................................................................................................ 13
7.6 Burst Termination ................................................................................................................ 13
7.7 Refresh Operation ............................................................................................................... 13
7.8 Power Down Mode .............................................................................................................. 13
7.9 Mode Register Operation .................................................................................................... 14
7.9.1 Burst Length field (A2 to A0) ..........................................................................................14
Publication Release Date:Jul. 04, 2007
- 1 - Revision A06
Datasheet pdf - http://www.DataSheet4U.net/

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W9412G6CH pdf
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W9412G6CH
3. KEY PARAMETERS
SYMBOL
tCK
DESCRIPTION
CLOCK
TIME
CYCLE CL = 2
MIN./MAX.
Min.
-45
-
CL = 2.5 Min.
-
CL = 3
Min. 4.5 nS
tRAS
Active to Precharge Command
Period
Min.
40 nS
tRC
Active to Ref/Active Command
Period
Min.
50 nS
IDD1 Operation Current (Single bank)
Max. 140mA
IDD4 Burst Operation Current
Max. 180mA
IDD6 Self-Refresh Current
Max.
3 mA
-5
7.5 nS
6 nS
5 nS
40 nS
50 nS
140mA
180mA
3 mA
-6
7.5 nS
6 nS
6 nS
42 nS
54 nS
130mA
170mA
3 mA
-75
7.5 nS
7.5 nS
7.5 nS
45 nS
60 nS
120mA
160mA
3 mA
-5-
Publication Release Date: Jul. 04, 2007
Revision A06
Datasheet pdf - http://www.DataSheet4U.net/

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W9412G6CH
7.2.10 No-Operation Command
( RAS = “H”, CAS = “H”, WE = “H”)
The No-Operation command simply performs no operation (same command as Device Deselect).
7.2.11 Burst Read Stop Command
( RAS = “H”, CAS = “H”, WE = “L”)
The Burst stop command is used to stop the burst operation. This command is only valid during a
Burst Read operation.
7.2.12 Device Deselect Command
( CS = “H”)
The Device Deselect command disables the command decoder so that the RAS , CAS , WE and
Address inputs are ignored. This command is similar to the No-Operation command.
7.2.13 Auto Refresh Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “H”, BS0, BS1, A0 to A11 = Don’t Care)
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS–
BEFORE–RAS (CBR) refresh in previous DRAM types. This command is non persistent, so it
must be issued each time a refresh is required.
The refresh addressing is generated by the internal refresh controller. This makes the address
bits ”Don’t Care” during an AUTO REFRESH command. The DDR SDRAM requires AUTO RE-
FRESH cycles at an average periodic interval of tREFI (maximum).
To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the
absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be
posted to any given DDR SDRAM, and the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command is 8 * tREFI.
7.2.14 Self Refresh Entry Command
( RAS = “L”, CAS = “L”, WE = “H”, CKE = “L”, BS0, BS1, A0 to A11 = Don’t Care)
The SELF REFRESH command can be used to retain data in the DD SDRAM, even if the rest of
the system is powered down. When in the self refresh mode, the DDR SDRAM retains data
without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF
REFRESH, and is automatically enabled upon exiting SELF REFRESH. Any time the DLL is
enabled a DLL Reset must follow and 200 clock cycles should occur before a READ command
can be issued. Input signals except CKE are “Don’t Care” during SELF REFRESH. Since CKE is
an SSTL_2 input, VREF must be maintained during SELF REFRESH.
- 11 -
Publication Release Date: Jul. 04, 2007
Revision A06
Datasheet pdf - http://www.DataSheet4U.net/

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