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PDF MAX11060 Data sheet ( Hoja de datos )
| Número de pieza | MAX11060 | |
| Descripción | (MAX11040K / MAX11060) Sigma-Delta ADCs | |
| Fabricantes | Maxim Integrated Products | |
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www.DataSheet.co.kr
19-5741; Rev 2; 11/11
EVAALVUAAILTAIOBNLEKIT
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
General Description
The MAX11040K/MAX11060 are 24-/16-bit, 4-channel,
simultaneous-sampling, sigma-delta analog-to-digital
converters (ADCs). The devices allow simultaneous
sampling of as many as 32 channels using a built-in
cascade feature to synchronize as many as eight
devices. The serial interface of the devices allows read-
ing data from all the cascaded devices using a single
command. Four modulators simultaneously convert
each fully differential analog input with a programmable
data output rate ranging from 0.25ksps to 64ksps. The
devices achieve 106dB SNR at 16ksps and 117dB SNR
at 1ksps (MAX11040K). The devices operate from a
single +3V supply. The differential analog input range is
±2.2V when using the internal reference; an external
reference is optional. Each input is overvoltage protect-
ed up to ±6V without damage. The devices use an
internal crystal oscillator or an external source for clock.
The devices are compatible with SPI™, QSPI™,
MICROWIRE™, and DSP-compatible 4-wire serial inter-
faces. An on-board interface logic allows one serial inter-
face (with a single chip select) to control up to eight
cascaded devices or 32 simultaneous sampling analog
input channels.
The devices are ideally suited for power-management
systems. Each channel includes an adjustable sam-
pling phase enabling internal compensation for phase
shift due to external dividers, transformers, or filters at
the inputs. The output data rate is adjustable with a
0.065% resolution (at 16ksps or below) to track the
varying frequency of a periodic input. A SYNC input
allows periodic alignment of the conversion timing of
multiple devices with a remote timing source.
The devices are available in a 38-pin TSSOP package speci-
fied over the -40°C to +105°C industrial temperature range.
Applications
Power-Protection Relay Equipment
Multiphase Power Systems
Industrial Data-Acquisition Systems
Medical Instrumentation
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX11040KGUU+ -40°C to +105°C 38 TSSOP
MAX11060GUU+ -40°C to +105°C 38 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Features
o Four Fully Differential Simultaneously Sampled
Channels
o Cascadable for Up to 32 Channels of
Simultaneous Sampling
o 106dB (MAX11040K) SNR at 16ksps
o 117dB (MAX11040K) SNR at 1ksps
o 0.25% Error Over a 1000:1 Dynamic Range,
Processed Over 16.7ms (MAX11040K)
o ±2.2V Full-Scale Input Range
o ±6V Overvoltage Protected Inputs
o Internal Crystal Oscillator
o 2.5V, 50ppm/°C Internal Reference or External
Reference
o Programmable Output Data Rate
0.25ksps to 64ksps Range
0.065% Resolution
o Programmable Sampling Phase
0 to 333µs Delay in 1.33µs Steps
o SPI-/QSPI-/MICROWIRE-/DSP-Compatible 4-Wire
Serial Interface
o Cascadable Interface Allows Control of Up to
Eight Devices with a Single CS Signal
o 3.0V to 3.6V Analog Supply Voltage
o 2.7V to VAVDD Digital Supply Voltage
o 38-Pin TSSOP Package
Functional Diagram
AIN0+
AIN0-
REF0
AIN1+
AIN1-
REF1
AIN2+
AIN2-
REF2
AIN3+
AIN3-
REF3
REFIO
OVRFLW FAULT
24-/16-BIT
ADC
DIGITAL
FILTER
24-/16-BIT
ADC
24-/16-BIT
ADC
DIGITAL
FILTER
DIGITAL
FILTER
REGISTERS AND
DIGITAL
CONTROL
24-/16-BIT
ADC
DIGITAL
FILTER
SERIAL
INTERFACE
SYNC
DRDYIN
DRDYOUT
CASCIN
CASCOUT
CS
SCLK
DIN
DOUT
AGND
2.5V
REFERENCE
CRYSTAL
OSCILLATOR
MAX11040K
MAX11060
XIN XOUT CLKOUT
DGND
MICROWIRE is a trademark of National Semiconductor Corp.
SPI/QSPI are trademarks of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.0V to +3.6V, VDVDD = +2.7V to VAVDD, fXIN CLOCK = 24.576MHz, fOUT = 16ksps, VREFIO = +2.5V (external), CREFIO =
CREF0 = CREF1 = CREF2 = CREF3 = 1μF to AGND, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SCLK Rise to DOUT Valid
CS Fall to DOUT Enable
CS Rise to DOUT Disable
CS Pulse Width
CASCIN-to-SCLK Rise Setup
SCLK Rise to CASCOUT Valid
SYNC Pulse Width
XIN Clock Pulse Width
DRDYIN to DRDYOUT
XIN Clock to DRDYOUT Delay
XIN Clock Period
XIN Clock to SYNC Setup
SYNC to XIN Clock Hold
XIN-to-CLKOUT Delay
Power-On Reset Delay
SYMBOL
tDOT
tDOE
tDOD
tCSW
tSC
tCOT
CONDITIONS
CLOAD = 30pF
CLOAD = 100pF
CLOAD = 30pF
CLOAD = 30pF
CLOAD = 100pF
tSYN
tXPW
tDRDY
tXDRDY
tXP
tSS
tHS
tXCD
CLOAD = 30pF
DRDYIN = DGND
(Note 12)
(Note 12)
(Note 13)
MIN TYP MAX UNITS
1.5 10 16
< 16
ns
0.3 20 ns
0.7 16 ns
16 ns
16 ns
20 ns
XIN
2 Clock
Cycles
16 ns
20 ns
40 ns
40 ns
16 ns
5 ns
40 ns
< 1 ms
Note 1: Devices are production tested at +105°C. Specifications to -40°C are guaranteed by design.
Note 2: Tested at VAVDD = VDVDD = +3.0V.
Note 3: Integral nonlinearity is the deviation of the analog value at any code from its ideal value after the offset and gain errors are
removed.
Note 4: Offset nulled.
Note 5: Offset and gain drift defined as change in offset and gain error vs. full scale.
Note 6: Noise measured with AIN_+ = AIN_- = AGND.
Note 7: Relative accuracy is defined as the difference between the actual RMS amplitude and the ideal RMS amplitude of a 62.5Hz
sine wave, measured over one cycle at a 16ksps data rate, expressed as a fraction of the ideal RMS amplitude. The rela-
tive accuracy specification refers to the maximum error expected over 1 million measurements. Calculated from SNR. Not
production tested.
Note 8: Latency is a function of the sampling rate and XIN clock.
Note 9: Voltage levels below the positive fault threshold and above the negative fault threshold, relative to AGND on each individ-
ual AIN_+ and AIN_- input, do not trigger the analog input protection circuitry.
Note 10: Test performed using RXD MP35.
Note 11: All digital inputs at DGND or DVDD.
Note 12: SYNC is captured by the subsequent XIN clock if this specification is violated.
Note 13: Delay from DVDD exceeds 2.0V until digital interface is operational.
_______________________________________________________________________________________ 5
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
24-/16-Bit, 4-Channel, Simultaneous-Sampling,
Cascadable, Sigma-Delta ADCs
Pin Description (continued)
PIN NAME
FUNCTION
Active-Low Data Ready Output. When DRDYIN = 0, DRDYOUT outputs a logic-low to indicate the
22 DRDYOUT availability of a new conversion result. DRDYOUT transitions high at the next CS falling edge or when
DRDYIN = 1. See the Multiple Device Connection section.
Active-Low Data Ready Input. A logic-high at DRDYIN causes DRDYOUT to output a logic-high. When
23 DRDYIN DRDYIN = 0, DRDYOUT outputs a logic-low when a new conversion result is available. See the Multiple
Device Connection section. Connect DRDYIN to DGND when not daisy chaining multiple devices.
Sampling Synchronization Input. The falling edge of SYNC aligns sampling and output data so that
24
SYNC
multiple devices sample simultaneously. Synchronize multiple devices running from independent crystals
by connecting DRDYOUT of the last device in the chain to the SYNC inputs of all devices in the chain.
Connect SYNC to DGND for single device operation. See the Multiple Device Connection section.
Crystal Oscillator Output. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
25 XOUT when using the internal oscillator. Leave XOUT unconnected when driving with an external frequency. See
the Crystal Oscillator section.
Crystal Oscillator/Clock Input. Connect a 24.576MHz external crystal or resonator between XIN and XOUT
26 XIN when using the internal oscillator or drive XIN with an external clock and leave XOUT unconnected. See
the Crystal Oscillator section.
30
AVDD
Positive Analog Supply Voltage. Bypass to AGND with a 1μF capacitor in parallel with a 0.01μF capacitor
as close as possible to the device.
32 REF3 ADC3 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
33 AIN3+ Positive Analog Input Channel 3
34 AIN3- Negative Analog Input Channel 3
36 REF2 ADC2 Buffered Reference Voltage. Bypass with a 1μF capacitor to AGND.
37 AIN2+ Positive Analog Input Channel 2
38 AIN2- Negative Analog Input Channel 2
______________________________________________________________________________________ 11
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MAX11060.PDF ] | |
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