PDF ICS93701 Data sheet ( Hoja de datos )

Número de pieza	ICS93701
Descripción	DDR Phase Lock Loop Clock Driver
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet.co.kr Integrated Circuit Systems, Inc. ICS9370 1 DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Product Description/Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz): <75ps • CYCLE - CYCLE jitter (66MHz):<120ps • CYCLE - CYCLE jitter (>100MHz):<65ps • OUTPUT - OUTPUT skew: <100ps • DUTY CYCLE: 49.5% - 50.5% • Slew rate: 1V/ns - 2V/ns Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT CLK_INC VDDI2C AVDD AGND GND CLKC3 CLKT3 VDD CLKT4 CLKC4 GND 1 48 GND 2 47 CLKC5 3 46 CLKT5 4 45 VDD 5 44 CLKT6 6 43 CLKC6 7 42 GND 8 41 GND 9 40 CLKC7 10 39 CLKT7 11 38 VDD 12 37 SDATA 13 36 FB_INC 14 35 FB_INT 15 34 VDD 16 33 FB_OUTT 17 32 FB_OUTC 18 31 GND 19 30 CLKC8 20 29 CLKT8 21 28 VDD 22 27 CLKT9 23 26 CLKC9 24 25 GND 48-Pin TSSOP Block Diagram SCLK SDATA Control Logic FB_INT FB_INC CLK_INC CLK_INT PLL 0417B—10/29/02 FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 Functionality AVDD 2.5V (nom) 2.5V (nom) 2.5V (nom) INPUTS CLK_INT CLK_INC LH HL <20MHz)(1) OUTPUTS CLKT CLKC FB_OUTT LH L HL H ZZ Z FB_OUTC H L Z PLL State on on off Datasheet pdf - http://www.DataSheet4U.net/ 1 page www.DataSheet.co.kr ICS9370 1 Recommended Operating Condition (see note1) TA = 0 - 85oC; Supply Voltage AVDD, VDD = 2.5V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Analog/core Supply Voltage Input voltage level Input differential-pair voltage swing1 VDDQ, AVDD VDDI2C VIL VIH VID DC - CLKT, FB_INT AC - CLKT, FB_INT 2.3 2.3 -0.3 0.4 0.36 0.5 Input differential crossing voltage VIX 0.45x(VIH-VIL) TYP 2.5 0 0.71 MAX 2.7 3.6 VDD-0.4 VDD+0.3 VDDQ +0.6 VDDQ +0.6 0.55x(VIH-VIL) UNITS V V V V V V Output differential crossing voltage VOX VDDQ/2 -0.2 1.25 1 Differential input signal voltage specifies the differential voltage [VTR - VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. VDDQ/2 +0.2 V Timing Requirements TA = 0 - 85oC; Supply Voltage AVDD, VDD = 2.5V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Max clock frequency Application Frequency Range freqop freqApp 2.5V+0.2V @ 25oC 2.5V+0.2V @ 25oC 33 60 Input clock duty cycle dtin 40 CLK stabilization TSTAB from VDD = 3.3V to 1% target freq. MAX 270 170 60 100 UNITS MHz MHz % µs 0417B—10/29/02 5 Datasheet pdf - http://www.DataSheet4U.net/ 5 Page

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