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PDF LC8784C8PB Data sheet ( Hoja de datos )

Número de pieza LC8784C8PB
Descripción 8-bit ETR Microcontroller
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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Ordering number : ENA1795
LC878496PB,LC8784C8PB
LC8784G0PB,LC8784G1PB
LC8784J2PB,LC8784J3PB
LC8784M4PB,LC8784P6PB
LC8784P7PB
CMOS IC
FROM 256K byte, RAM 12K byte on-chip
8-bit ETR Microcontroller
Overview
The LC8784XXPB series is an 8-bit ETR microcomputer that, centered around a CPU running at a minimum bus cycle
time of 74.07 ns (CF = 13.5MHz), integrate on a single chip a number of hardware features such as direct control
function of CD mechanism and CD-DSP for car audio, 256K-byte ROM (max), 12K-byte RAM (max), two
sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer
serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities),
an asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 10-channel
AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt
feature.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
Ver.1.07
20211HKPC 20100618-S00013, S00012, S00011, S00010, S00009, S00008, S00007, S00006, S00005 No.A1795-1/29
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LC8784C8PB pdf
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LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB
Standby Function
HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by system reset, detection VDET0 or occurrence of interrupt.
HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF oscillators, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the Reset pin to the lower level.
(2) Voltage descent detection (VDET1)
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(4) Having an interrupt source established at port 0.
X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF oscillators, and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when X’tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the Reset pin to the low level.
(2) Voltage descent detection (VDET0)
(3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(4) Having an interrupt source established at port 0.
(5) Having an interrupt source established in the base timer circuit.
Reset
External reset
Voltage descent detection (VDET0, VDET1) reset circuit (internal)
Shipping Form
QIP100E (Lead Free Product)
Flash ROM Version
LC87F83P7PB
LC87F83P7PBU (User writing)
No.A1795-5/29
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LC8784C8PB arduino
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LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Frequency tSCK(3)
Pins/
Remarks
SCK1(P15)
Conditions
See Fig. 2.
VDD[V]
Low level
pulse width
High level
pulse width
Frequency
tSCKL(3)
tSCKH(3)
tSCK(4)
Low level
pulse width
High level
pulse width
Data setup time
tSCKL(4)
tSCKH(4)
tsDI(2)
Data hold time thDI(2)
3.0 to 5.5
SCK1(P15) • CMOS output selected.
• See Fig. 2.
3.0 to 5.5
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 2.
3.0 to 5.5
min
2
Specification
typ max
1
1
2
1/2
1/2
0.03
0.03
unit
tCYC
tSCK
Output
tdD0(4)
SO1(P13), • Must be specified with respect to
delay time
SB1(P14)
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
3.0 to 5.5
change in open drain output
mode.
• See Fig. 2.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
μs
(1/3)tCYC
+0.05
No.A1795-11/29
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