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PDF LC749880T Data sheet ( Hoja de datos )
| Número de pieza | LC749880T | |
| Descripción | Image controller LSI | |
| Fabricantes | Sanyo Semicon Device | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LC749880T (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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www.DataSheet.co.kr
Ordering number : ENA1186
CMOS IC
LC749880T Silicon gate
Image controller LSI for LCD-TV
Overview
LC749880T is an LSI to display the converted NTSC/PAL analog video signals in the liquid crystal panel of maximum
VGA size.
This product performs A/D conversion, YC separation, color decoding, IP conversion, resolution conversion, and various
enhancements according to the panel.
When combined with a microcomputer and LCD panel, this product can readily makes up a video signal processing
circuit for flat panel display
Features
(1) Analog input
• 3ch A/D converter incorporated
• CVBS, S-Video,YCbCr/YPbPr input
(2) YC separation video decoder
• Adaptive 3-line comb filter
• AGC, ACC
(3) Resolution conversion
• Interlace - progressive conversion
• Expansion/compression possible independently in horizontal and vertical directions
(4) Enhancing functions
• Adjusting the TV picture quality: Contour correction, color, hue, luminance, contrast
• Adjusting the panel display picture quality: White balance, black balance,γ correction
• Color exciter (6-phase RGBYMC independent saturation adjustment)
• Shadow adjuster (emphaizing the three-dimensionality)
• Dither (8bit/6bit)
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
51408HKIM 20080319-S00007 No.A1186-1/17
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
LC749880T
Continued from preceding page.
Signal type
No. of pins
Pin symbol
Description
Remarks
TCON signal
(1)
(GRST)
TCON signal
(GPIO pin)
When MODE=0, the gate reset signal output/clamp
pulse output/PWM3 output selectable through register selection
When MODE≠0, the gate reset signal output/clamp
pulse output selectable through register selection
GRST: Pulse width, position, and polarity reversal possible
1 FLM
When MODE=0, 1, and 2, gate start pulse signal output
Pulse width, position, polarity reversal possible. Hi-Z
when FLM2 is used
1 OE
When MODE=0, 1, and 2, gate output enable signal output.
Pulse width, position, polarity reversal possible.
1 CPV
When MODE=0, 1, and 2, gate clock signal output.
Pulse width, position, polarity reversal possible.
1 STRB
When MODE=0, 1, and 2, source strobe signal output.
Pulse width, position, polarity reversal possible.
1 SP
When MODE=0, 1, and 2, source start pulse signal output.
Pulse width, position, polarity reversal possible. Hi-Z
when SP2 is used
1 DEXR
When MODE=0, 1, and 2, source picture element reversal signal
output.
When MODE=0, DEXR output of odd-numbered picture
elements
1 POL
When MODE=0, 1, and 2, source voltage polarity
selection signal output.
Position adjustment, 1 line/2 line reversal and 1 frame/2
frame reversal possible
(1) (TIM0)
When MODE=0, 1, and 2, FLM2 output through register setting
Pulse width, position, polarity reversal possible. Hi-Z
when FLM is used
(1) (TIM1)
When MODE=0,1, and 2, SP2 output through register setting
Pulse width, position, polarity reversal possible. Hi-Z
when SP2 is used
(1) (TIM2)
When MODE=0, DEXR (DEXR_E) output of
even-numbered picture elements
Clock
1
DCLKO
Dot clock
Picture element clock output. Polarity reversal, 1/2
output possible
1 (DCLKO3) Clock
When MODE=0 and 1, clock output (3.357MHz)
1 XOUT
Crystal oscillator output pin
For OSD signal
1
VSO
OSD I/F
Vertical synchronizing signal output for OSD (To μ-CON)
Pulse width, position, polarity reversal possible.
1 HSO
Horizontal synchronizing signal output for OSD (To μ-CON)
Pulse width, position, polarity reversal possible.
1 DCLKO2
Picture-element clock output for OSD (To μ-CON)
Polarity reversal, 1/2 output possible
PWM output
(1)
(VP32)
PWM signal
(GPIO pin)
When MODE≠0, PWM1 output through register setting.
Pulse width, position, polarity reversal possible.
(1) (VP35)
When MODE≠0, PWM2 output/PWM3 output/clamp pulse output
selectable through register setting.
PWM2, 3: Pulse width, position, polarity reversal possible.
(1) (GRST)
When MODE=0, PWM3 output/GRST output/clamp pulse output
selectable through register setting
PWM3: Pulse width, position, polarity reversal possible.
Clamp pulse
(1)
(VP35)
Clamp pulse
(GPIO pin)
When MODE≠0, clamp pulse output/PWM2 output/PWM3 output
selectable through register setting
Clamp pulse: Pulse width and position adjustment possible.
(1) (GRST)
When MODE=0, clamp pulse output/GRST output/PWM3 output
selectable through register setting.
When MODE≠0, clamp pulse output/GRST output selectable
through register setting
Clamp pulse: Pulse width and position adjustment possible.
* The signals in parentheses show that one pin has multiple functions or acts as the I/O pin.
Selection can be made with the MODE pin or through register setting.
No.A1186-5/17
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
Pin Type
I/O type
A
Function
Analog I/O
B 5V withstand
Schmidt trigger
CMOS input*
C 5V withstand
With Pull-down
CMOS input*
D Oscillator circuit I/O
LC749880T
Equivalent circuit
Applicable pins
CRIN, VRT1, VRB1, CBIN, SC, VRT2, VRB2,
NBIAS, VREF1, SVO, YIN, SY, CVBS1,
CVBS2, VRT3, VRB3, VRTC, LPFO, LPFVDD,
CHAGPUP, VCOR
RESET,
VSI, HSI,
PDWN, SCL
SCANEN, SCANMOD, I2CSEL,
RIN, GIN, BIN, BLKIN, TEST,
MODE0, MODE1, MODE2
XIN, XOUT
E 8mA 3-STATE drive
CMOS output*
F 12mA 3-STATE drive
CMOS output*
G 8mA 3-STATE drive
CMOS I/O*
H 12mA 3-STATE drive
CMOS I/O*
*: 5V Tolerant
TIM0, TIM1, TIM2, VP00, VP01, VP02,
VP03, VP04, VP05, VP06, VP07, VP08,
VP09, VP10, VP11, VP12, VP13, VP14,
VP15, VP16, VP17, VP18, VP19, VP20,
VP21, VP22, VP23, HSO, VSO
DCLKO2, DCLKO
GRST, FLM, OE, CPV, STRB, SP, DEXR,
POL, VP24, VP25, VP26, VP27, VP28, VP29,
VP30, VP31, VP32, VP33, VP34, VP35,
SDA
DCLKO3
No.A1186-11/17
Datasheet pdf - http://www.DataSheet4U.net/
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| Páginas | Total 17 Páginas | |
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