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PDF LC87F8364AU Data sheet ( Hoja de datos )

Número de pieza LC87F8364AU
Descripción 8-bit ETR Microcontroller
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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Ordering number : ENA1780
LC87F83C8A/AU
LC87F8396A/AU
LC87F8364A/AU
CMOS IC
FROM 128K byte, RAM 6K byte on-chip
8-bit ETR Microcontroller
Overview
The LC87F83C8A/AU/96A/AU/64A/AU is an 8-bit ETR microcomputer that, centered around a CPU running at a
minimum bus cycle time of 74.04 ns, integrate on a single chip a number of hardware features such as 128K-bytes of
flash ROM maximum (onboard rewritable), 6K-bytes of RAM maximum, Onchip debugging, direct control of
necessary CD mechanism and CD-DSP for car audio, in the radio reception, the on-chip high-performance PLL circuit
provides a high-speed Lock-Up circuit to search for alternative frequency of RDS in a short time, the ability to control
the C/N characteristics of a local oscillator, and the high S/N through the direct PLL configuration, two sophisticated
16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a
time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an
asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 10-channel
AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt
feature.
ROM for each model/Table RAM capacity
Type No.
LC87F8364A/AU
LC87F8396A/AU
LC87F83C8A/AU
Flash ROM (byte)
64K
96K
128K
RAM (byte)
4K
6K
6K
FeFalatsuh rReOsM
Single 5V power supply, on-board writeable
Block erase in 128 byte units
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer's products or
equipment.
Ver.1.03
20211HKPC 20100603-S00007, S00009, S00010, S00012, S00013, S00014 No.A1780-1/31
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LC87F83C8A/C8AU/96A/96AU/64A/64AU
Reset
External reset
Voltage descent detection (VDET0, VDET1) reset circuit (internal)
Onchip Debugging Function
Permits software debugging with the test device installed on the target board.
Shipping Form
QIP100E (Lead Free Product)
Flash ROM Version
LC87F83C8A/96A/64A
LC87F83C8AU/96AU/64AU (User writing)
No.A1780-5/31
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LC87F83C8A/C8AU/96A/96AU/64A/64AU
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Frequency tSCK(3)
Pins/
Remarks
SCK1(P15)
Conditions
See Fig. 2.
VDD[V]
Low level
pulse width
High level
pulse width
Frequency
tSCKL(3)
tSCKH(3)
tSCK(4)
Low level
pulse width
High level
pulse width
Data setup time
tSCKL(4)
tSCKH(4)
tsDI(2)
Data hold time thDI(2)
3.0 to 5.5
SCK1(P15) • CMOS output selected.
• See Fig. 2.
3.0 to 5.5
SI1(P14),
SB1(P14)
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 2.
3.0 to 5.5
min
2
1
1
2
0.03
0.03
Specification
typ max
1/2
1/2
unit
tCYC
tSCK
Output
tdD0(4)
SO1(P13), • Must be specified with respect to
delay time
SB1(P14)
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
3.0 to 5.5
change in open drain output
mode.
• See Fig. 2.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
μs
(1/3)tCYC
+0.05
No.A1780-11/31
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