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PDF LC87F5R96B Data sheet ( Hoja de datos )

Número de pieza LC87F5R96B
Descripción 8-bit 1-chip Microcontroller
Fabricantes Sanyo Semicon Device 
Logotipo Sanyo Semicon Device Logotipo



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Ordering number : ENA0928
LC87F5R96B
CMOS IC
FROM 98K byte, RAM 4096 byte on-chip
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F5R96B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 83.3ns, integrates on a single chip a number of hardware features such as 98K-byte flash ROM (onboard
programmable), 4096-byte RAM, On-chip debugging function, sophisticated 16-bit timers/counters (may be divided into
8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface (with
automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full
duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a 27-source
10-vector interrupt feature.
Features
„Flash ROM
Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
Block-erasable in 128 byte units
100352 × 8 bits (Address: 00000H to 17FFFH, 1F800H to 1FFFFH)
„RAM
4096 × 9 bits
„Minimum Bus Cycle Time
83.3ns (12MHz)
125ns (8MHz)
500ns (2MHz)
VDD=2.8 to 5.5V
VDD=2.5 to 5.5V
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
„Minimum Instruction Cycle Time (tCYC)
250ns (12MHz)
375ns (8MHz)
1.5µs (2MHz)
VDD=2.8 to 5.5V
VDD=2.5 to 5.5V
VDD=2.2 to 5.5V
„Ports
Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
Normal withstand voltage input port
Dedicated oscillator ports
Reset pins
Power pins
46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Ver.1.00
91207HKIM 20070810-S00010 No. A0928-1/22
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LC87F5R96B pdf
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Package Dimensions
unit : mm (typ)
3159A
48
49
17.2
14.0
33
32
LC87F5R96B
64
1
(1.0)
0.8
17
16
0.35
0.15
SANYO : QIP64E(14X14)
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN/NKIN
P73/INT3/T0IN
RES
XT1/AN10
XT2/AN11
VSS1
CF1
CF2
VDD1
P80/AN0
P81/AN1
P82/AN2
P10/SO0
P11/SI0/SB0
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
LC87F5R96B
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P32/UTX1
P33/URX1
P34/UTX2
P35/URX2
P36
P37
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN/INT7
P23/INT4/T1IN
P22/INT4/T1IN
P21/INT4/T1IN
P20/INT4/T1IN/INT6
P07/T7O
P06/T6O
Top view
SANYO: QIP64E(14×14) “Lead-free Type”
No.A0928-5/22
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LC87F5R96B arduino
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LC87F5R96B
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Operating
supply voltage
(Note2-1)
Symbol
VDD(1)
Pins/Remarks
VDD1=VDD2=VDD3
Conditions
0.245µstCYC200µs
0.367µstCYC200µs
1.47µstCYC200µs
VDD[V]
min
2.8
2.5
2.2
Specification
typ max
5.5
5.5
5.5
unit
Memory
sustaining
supply voltage
VHD
VDD1=VDD2=VDD3
RAM and register contents
sustained in HOLD mode
2.0 5.5
High level input
voltage
VIH(1)
Ports 1, 2
P71 to P73
P70 port input/
2.2 to 5.5
0.3VDD
+0.7
VDD
interrupt side
VIH(2)
Ports 0, 8, 3, C
PWM2, PWM3
2.2 to 5.5
0.3VDD
+0.7
VDD
VIH(3)
Low level input
voltage
VIH(4)
VIL(1)
Port P70 watchdog
timer side
XT1, XT2, CF1,RES
Ports 1, 2
P71 to P73
P70 port input/
Interrupt side
2.2 to 5.5
2.2 to 5.5
4.0 to 5.5
0.9VDD
0.75VDD
VSS
2.2 to 4.0
VSS
VDD
VDD
0.1VDD
+0.4
0.2VDD
V
VIL(2)
Ports 0, 8, 3, C
PWM2, PWM3
4.0 to 5.5
VSS
0.15VDD
+0.4
VIL(3)
Instruction cycle
time
(Note2-2)
VIL(4)
tCYC
Port 70 watchdog
timer side
XT1, XT2, CF1, RES
2.2 to 5.5
2.2 to 5.5
2.2 to 5.5
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
VSS
VSS
VSS
0.245
0.367
1.47
0.2VDD
0.8VDD
-1.0
0.25VDD
200
200
200
µs
External system
clock frequency
FEXCF(1)
CF1
• CF2 pin open
• System clock frequency
division rate=1/1
• External system clock
duty=50±5%
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.1
0.1
0.1
12
8
2
MHz
• CF2 pin open
• System clock frequency
division rate=1/2
2.8 to 5.5
2.5 to 5.5
2.2 to 5.5
0.2
0.1
0.1
24.4
16
4
Oscillation
frequency
range
(Note2-3)
FmCF(1) CF1, CF2
FmCF(2) CF1, CF2
12MHz ceramic oscillation
See Fig. 1.
8MHz ceramic oscillation
See Fig. 1.
2.8 to 5.5
2.5 to 5.5
12
8
FmCF(3) CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
2.2 to 5.5
MHz
4
FmRC
Internal RC oscillation
2.2 to 5.5
0.3 1.0
2.0
FmMRC
Frequency variable RC
oscillation source oscillation
2.5 to 5.5
16
FsX’tal
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
2.2 to 5.5
32.768
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0928-11/22
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