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PDF NL6448BC33-63D Data sheet ( Hoja de datos )
| Número de pieza | NL6448BC33-63D | |
| Descripción | Display Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL6448BC33-63D
26cm (10.4 Type)
VGA
LVDS interface (1port)
PRELIMINARY DATA SHEET
DOD-PD-1288 (2nd edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-PD-1278(1).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PD-1288 (2nd edition)
Published date: January 2006 CP(N)
1 © NEC LCD Technologies, Ltd.
2005, 2006 All rights reserved.
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NL6448BC33-63D
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
Response time
Luminance
Signal system
Power supply voltage
Backlight
Power consumption
211.2 (H) × 158.4 (V) mm
26cm (10.4 inches)
a-Si TFT active matrix
16,777,216 colors (At 8-bit input, FRC terminal= High)
262,144 colors (At 6-bit input, FRC terminal= Low or Open)
640 (H) × 480 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.11 (H) × 0.33 (V) mm
0.33 (H) × 0.33 (V) mm
243.0 (W) × 185.1 (H) × 10.5 (D) mm (typ.)
475g (typ.)
TBD (typ.)
At the contrast ratio ≥10:1
• Horizontal: Right side 80° (typ.), Left side 80° (typ.)
• Vertical: Up side 80° (typ.), Down side 60° (typ.)
At DPS= Low or open: Normal scan
• Viewing direction without image reversal: up side (12 o'clock)
• Viewing direction with contrast peak: down side (6 o'clock)
• Viewing angle with optimum grayscale (γ=2.2): normal axis (perpendicular)
Antiglare
3H (min.) [by JIS K5400]
At LCD panel center
40% (typ.) [against NTSC color space]
Ton+Toff (10%←→ 90%)
25ms (typ.)
At IBL= 5.0mArms / lamp
450cd/m2 (typ.)
LVDS 1port (Receiver: THC63LVDF84B, THine Electronics Inc. or equivalent)
[8bit/6bit digital signals for data of RGB colors, Dot clock (CLK),
Data enable (DE)]
LCD panel signal processing board: 3.3V
Edge light type: 2 cold cathode fluorescent lamps
Replaceable part
• Lamp holder set: Type No. TBD
Recommended inverter (Option)
• Inverter: Type No. TBD
At IBL=5.0mArms / lamp, Checkered flag pattern
TBD W (typ., Power dissipation of the inverter is not included.)
PRELIMINARY DATA SHEET DOD-PD-1288 (2nd edition)
5
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NL6448BC33-63D
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VCC
Note1
0V
ON
3.0V
10µs ≤Tr< 50ms
Display signals*,
Function signals
Note2
0V
0ms <t< 35ms
VALID period
OFF ON
0.3V
Toff≥ TBD ms
0ms <t< 35ms
* These signals should be measured at the terminal of 100Ω resistance.
Note1: In terms of voltage variation (voltage drop) while VCC rising edge is below 3.0V, a protection
circuit may work, and then this product may not work.
Note2: Display signals (D0+/-, D1+/-, D2+/-, D3+/- and CK+/-) and function signals (DPS and FRC)
must be Low or High-impedance, exclude the VALID period (See above sequence diagram), in
order to avoid that internal circuits is damaged.
If some of display and function signals of this product are cut while this product is working, even
if the signal input to it once again, it might not work normally. VCC should be cut when the
display and function signals are stopped.
4.4.2 Inverter (Option)
Display signals,
Function signals
Note1
Note2
VALID period
VDDB
Note1: These are the display and function signals for LCD panel signal processing board.
Note2: The backlight should be turned on within the valid period of display and function signals, in order
to avoid unstable data display.
PRELIMINARY DATA SHEET DOD-PD-1288 (2nd edition)
11
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