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PDF FM25L512 Data sheet ( Hoja de datos )
| Número de pieza | FM25L512 | |
| Descripción | 3V F-RAM Memory | |
| Fabricantes | Ramtron | |
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Preliminary
FM25L512
512Kb FRAM Serial 3V Memory
Features
512K bit Ferroelectric Nonvolatile RAM
• Organized as 65,536 x 8 bits
• Unlimited Read/Write Cycles
• 10 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process
Very Fast Serial Peripheral Interface - SPI
• Up to 20 MHz Frequency
• Direct Hardware Replacement for EEPROM
• SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)
Write Protection Scheme
• Hardware Protection
• Software Protection
Low Power Consumption
• Low Voltage Operation 3.0V – 3.6V
• 20 µA Standby Current
Industry Standard Configurations
• Industrial Temperature -40°C to +85°C
• 8-pin “Green”/RoHS TDFN Package
• Footprint Compatible with SOIC-8 (see pg 12)
Description
The FM25L512 is a 512-kilobit nonvolatile memory
employing an advanced ferroelectric process. A
ferroelectric random access memory or FRAM is
nonvolatile and performs reads and writes like a
RAM. It provides reliable data retention for 10 years
while eliminating the complexities, overhead, and
system level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike serial EEPROMs, the FM25L512 performs
write operations at bus speed. No write delays are
incurred. The next bus cycle may commence
immediately without the need for data polling. The
next bus cycle may start immediately. In addition, the
product offers virtually unlimited write endurance.
Also, FRAM exhibits much lower power
consumption than EEPROM.
These capabilities make the FM25L512 ideal for
nonvolatile memory applications requiring frequent
or rapid writes or low power operation. Examples
range from data collection, where the number of
write cycles may be critical, to demanding industrial
controls where the long write time of EEPROM can
cause data loss.
The FM25L512 provides substantial benefits to users
of serial EEPROM as a hardware drop-in
replacement. The FM25L512 uses the high-speed SPI
bus, which enhances the high-speed write capability
of FRAM technology. Device specifications are
guaranteed over an industrial temperature range of
-40°C to +85°C.
This is a product that has fixed target specifications but are subject
to change pending characterization results.
Rev. 1.2
Aug. 2007
Pin Configuration
Top View
/CS 1
SO 2
8 VDD
7 /HOLD
/WP 3
VSS 4
6 SCK
5 SI
Pin Name
/CS
/WP
/HOLD
SCK
SI
SO
VDD
VSS
Function
Chip Select
Write Protect
Hold
Serial Clock
Serial Data Input
Serial Data Output
Supply Voltage (3.0 to 3.6V)
Ground
Ordering Information
FM25L512-DG 8-pin “Green”/RoHS TDFN
Ramtron International Corporation
1850 Ramtron Drive, Colorado Springs, CO 80921
(800) 545-FRAM, (719) 481-7000
www.ramtron.com
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FM25L512
Power Up to First Access
The FM25L512 is not accessible for a period of time
(10 ms) after power up. Users must comply with the
timing parameter tPU, which is the minimum time
from VDD (min) to the first /CS low.
Data Transfer
All data transfers to and from the FM25L512 occur in
8-bit groups. They are synchronized to the clock
signal (SCK), and they transfer most significant bit
(MSB) first. Serial inputs are registered on the rising
edge of SCK. Outputs are driven from the falling
edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25L512. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided into three categories. First, there are
commands that have no subsequent operations. They
perform a single function such as to enable a write
operation. Second are commands followed by one
byte, either in or out. They operate on the Status
Register. The third group includes commands for
memory transactions followed by address and one or
more bytes of data.
Table 1. Op-code Commands
Name Description
WREN Set Write Enable Latch
WRDI Write Disable
RDSR Read Status Register
WRSR Write Status Register
READ Read Memory Data
WRITE Write Memory Data
Op-code
0000 0110b
0000 0100b
0000 0101b
0000 0001b
0000 0011b
0000 0010b
WREN - Set Write Enable Latch
The FM25L512 will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the Status
Register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the Status
Register, called WEL, indicates the state of the
latch. WEL=1 indicates that writes are permitted.
Attempting to write the WEL bit in the Status
Register has no effect on the state of this bit. The
WEL bit will be automatically cleared on the rising
edge of /CS following a WRDI, a WRSR, or a
WRITE operation. This prevents further writes to
the Status Register or the FRAM array without
another WREN command. Figure 5 below illustrates
the WREN command bus configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the Status Register and verifying that WEL=0.
Figure 6 illustrates the WRDI command bus
configuration.
CS
SCK
01 2 3 4 5 6 7
SI 0 0 0 0 0 1 1 0
SO Hi-Z
Figure 5. WREN Bus Configuration
Rev. 1.2
Aug. 2007
Page 5 of 13
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Serial Data Bus Timing
FM25L512
/Hold Timing
CS
SCK
HOLD
SO
Power Cycle Timing
tHS
tHH
tHS
tHH
tHZ tLZ
Power Cycle Timing (TA = -40° C to + 85° C, VDD = 3.0V to 3.6V)
Symbol
Parameter
tPU Power Up (VDD min) to First Access (/CS low)
tPD Last Access (/CS high) to Power Down (VDD min)
tVR VDD Rise Time
tVF VDD Fall Time (applies only to VDD levels below 2V)
Notes
1. This parameter is characterized and not 100% tested.
2. Slope measured at any point on VDD waveform.
Rev. 1.2
Aug. 2007
Min Max Units Notes
10 - ms
0 - µs
50
- µs/V
1,2
1
- ms/V
1,2
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