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PDF RTL8169 Data sheet ( Hoja de datos )
| Número de pieza | RTL8169 | |
| Descripción | GIGABIT ETHERNET MEDIA ACCESS CONTROLLER | |
| Fabricantes | Realtek Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de RTL8169 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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RTL8169
REALTEK GIGABIT
ETHERNET MEDIA ACCESS
CONTROLLER
WITH POWER MANAGEMENT
RTL8169
1. Features........................................................................ 2
2. General Description .................................................... 3
3. Block Diagram............................................................. 4
4. Pin Assignments .......................................................... 5
5. Pin Description ............................................................ 6
5.1 Power Management/Isolation Interface ................. 6
5.2 PCI Interface .......................................................... 7
5.3 FLASH/BootPROM/EEPROM/MII Interface ....... 9
5.4 LED Interface....................................................... 10
5.5 GMII, TBI, PHY CP ............................................ 10
5.6 Clock and NC Pins............................................... 12
5.7 Power Pins ........................................................... 12
6. Register Descriptions ................................................ 13
6.1 DTCCR: Dump Tally Counter Command............ 15
6.2 FLASH: Flash Memory Read/Write .................... 16
6.3 ERSR: Early Rx Status......................................... 16
6.4 Command ............................................................. 17
6.5 TPPoll: Transmit Priority Polling......................... 17
6.6 Interrupt Mask...................................................... 18
6.7 Interrupt Status..................................................... 19
6.8 Transmit Configuration ........................................ 20
6.9 Receive Configuration ......................................... 21
6.10 9346CR: 93C46 (93C56) Command.................. 23
6.11 CONFIG 0.......................................................... 23
6.12 CONFIG 1.......................................................... 24
6.13 CONFIG 2.......................................................... 25
6.14 CONFIG 3.......................................................... 25
6.15 CONFIG 4.......................................................... 26
6.16 CONFIG 5.......................................................... 27
6.17 Multiple Interrupt Select .................................... 28
6.18 PHYAR: PHY Access ........................................ 28
6.19 TBICSR: Ten Bit Interface Control and Status .. 28
6.20 TBI_ANAR: TBI Auto-Negotiation Advertisement .. 29
6.21 TBI_LPAR:TBIAuto-NegotiationLinkPartnerAbility....... 29
6.22 PHYStatus: PHY(GMII or TBI) Status.............. 30
6.23 RMS: Receive (Rx) Packet Maximum Size ....... 30
6.24 C+CR: C+ Command......................................... 31
6.25 RDSAR: Receive Descriptor Start Address ....... 31
6.26 ETThR: Early Transmit Threshold..................... 31
6.27 Function Event ................................................... 32
6.28 Function Event Mask ......................................... 32
6.29 Function Preset State.......................................... 33
6.30 Function Force Event ......................................... 33
7. EEPROM (93C46 or 93C56) Contents ................... 34
7.1 EEPROM Registers.............................................. 35
7.2 EEPROM Power Management Registers............. 35
8. PCI Configuration Space Registers......................... 36
8.1 PCI Bus Interface ................................................. 36
8.1.1 Byte Ordering ............................................... 36
8.1.2 Interrupt Control........................................... 36
8.1.3 Latency Timer............................................... 36
8.1.4 64-Bit Data Operation .................................. 37
8.1.5 64-Bit Addressing......................................... 37
8.2 Bus Operation ...................................................... 37
8.2.1 Target Read................................................... 37
8.2.2 Target Write.................................................. 38
8.2.3 Master Read.................................................. 38
8.2.4 Master Write................................................. 39
8.2.5 Configuration Access ................................... 40
8.3 Packet Buffering .................................................. 40
8.3.1 Transmit Buffer Manager ............................. 40
8.3.2 Receive Buffer Manager............................... 40
8.3.3 Packet Recognition....................................... 40
8.4 PCI Configuration Space Table............................ 41
8.5 PCI Configuration Space Functions..................... 42
8.6 Default Value After Power-on (RSTB Asserted) . 46
8.7 Power Management functions.............................. 47
8.8 Vital Product Data (VPD) .................................... 49
9. Functional Description ............................................. 50
9.1 Transmit & Receive Operations........................... 50
9.1.1 Transmit........................................................ 50
9.1.2 Receive ......................................................... 55
9.2 Loopback Operation............................................. 58
9.3 Collision............................................................... 58
9.4 Flow Control ........................................................ 58
9.4.1. Control Frame Transmission ....................... 58
9.4.2. Control Frame Reception ............................ 58
9.5 Memory Functions ............................................... 59
9.5.1 Memory Read Line (MRL) .......................... 59
9.5.2 Memory Read Multiple (MRM) ................... 59
9.5.3 Memory Write and Invalidate (MWI) .......... 60
9.5.4 Dual Address Cycle (DAC).......................... 60
9.6 LED Functions ..................................................... 61
9.6.1 Link Monitor ................................................ 61
9.6.2 Rx LED ........................................................ 61
9.6.3 Tx LED......................................................... 62
9.6.4 Tx/Rx LED ................................................... 62
9.6.5 LINK/ACT LED........................................... 63
9.7 Physical Layer Interfaces ..................................... 64
9.7.1 Media Independent Interface (MII) .............. 64
9.7.2 Gigabit Media Independent Interface (GMII) ...... 64
9.7.3 Ten Bit Interface (TBI)................................. 64
9.7.4 MII/GMII Management Interface................. 64
10. Application Diagrams............................................. 65
10.1 10/100/1000Base-T Application ........................ 65
10.2 1000Base-X Application.................................... 65
11. Electrical Characteristics ....................................... 66
11.1 Temperature Limit Ratings................................. 66
11.2 DC Characteristics ............................................. 66
11.3 AC Characteristics ............................................. 67
11.3.1 FLASH/BOOT ROM Timing..................... 67
11.3.2 Serial EEPROM Interface Timing .............. 69
11.3.3 PCI Bus Operation Timing ......................... 70
11.3.4 MII Timing ................................................. 87
11.3.5 GMII Timing .............................................. 89
11.3.6 TBI Timing ................................................. 90
12. Mechanical Dimensions .......................................... 91
2002/03/27
1
Rev.1.21
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
4. Pin Assignments
131 VDD33
132 RSTPHYB
133 TBILBK
134 GND
135 TXD7
136 TXD6
137 TXD5
138 TXD4
139 TXD3
140 TXD2
141 TXD1
142 TXD0
143 TXEN
144 VDD33
145 GTXCLK
146 TX8
147 TXCLK
148 CRS
149 GND
150 GND
151 COL
152 RXER
153 NC
154 RXCLK1
155 NC
156 RXCLK
157 RXDV
158 RXD0
159 RXD1
160 RXD2
161 RXD3
162 RXD4
163 RXD5
164 RXD6
165 RXD7
166 VDD18
167 VDD33
168 CLOCK125
169 MDC
170 MDIO
171 GND
172 ISOLATEB
173 M66EN
174 INTAB
175 RSTB
176 CLK
177 GNTB
178 REQB
179 VDD33
180 AD31
181 AD30
182 AD29
183 AD28
184 GND
185 AD27
186 AD26
187 AD25
188 AD24
189 VDD33
190 CBE3B
191 IDSEL
192 AD23
193 AD22
194 AD21
195 GND
196 AD20
197 AD19
198 AD18
199 AD17
200 VDD33
201 AD16
202 CBE2B
203 FRAMEB
204 IRDYB
205 TRDYB
206 GND
207 DEVSELB
208 STOPB
1 PERRB
2 NC
3 SERRB
4 NC
5 PAR
6 NC
7 CBE1B
8 VDD33
9 AD15
10 AD14
11 AD13
12 AD12
13 GND
14 AD11
15 AD10
16 AD9
17 AD8
18 VDD33
19 CBE0B
20 AD7
21 AD6
22 AD5
23 GND
24 AD4
25 AD3
26 AD2
2002/03/27
RTL8169
5
RTL8169
130 OEB
129 WEB
128 ROMCSB
127 MD0
126 MD1
125 MD2
124 MD3
123 MD4
122 MD5
121 MD6
120 VDD18
119 MD7
118 LED0
117 GND
116 LED1
115 LED2
114 LED3
113 VDD33
112 MA16
111 MA15
110 MA14
109 MA13
108 NC
107 MA12
106 NC
105 MA11
104 MA10
103 NC
102 MA9
101 MA8
100 MA7
99 MA6
98 GND
97 MA5
96 MA4
95 MA3
94 GND
93 EECS
92 MA2
91 MA1
90 MA0
89 VDD33
88 LWAKE
87 PMEB
86 CLKRUNB
85 AD32
84 AD33
83 AD34
82 GND
81 AD35
80 AD36
79 AD37
78 AD38
77 VDD33
76 AD39
75 AD40
74 AD41
73 AD42
72 GND
71 GND
70 AD43
69 AD44
68 VDD18
67 AD45
66 AD46
65 VDD33
64 AD47
63 AD48
62 AD49
61 AD50
60 GND
59 AD51
58 AD52
57 AD53
56 AD54
55 VDD33
54 AD55
53 AD56
52 AD57
51 NC
50 AD58
49 NC
48 GND
47 NC
46 AD59
45 NC
44 AD60
43 AD61
42 AD62
41 VDD33
40 AD63
39 PAR64
38 CBE4B
37 CBE5B
36 GND
35 CBE6B
34 CBE7B
33 GND
32 REQ64B
31 ACK64B
30 VDD33
29 AD0
28 AD1
27 VDD18
Rev.1.21
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
TxD[7:0]/
Tx[7:0]
O
RxCLK/
RxCLK0
I
RxCLK1
RxER/
Rx[9]
I
I
RxDV/
Rx[8]
I
RxD[7:0]/
Rx[7:0]
I
COL
I
cont...
135-142
156
154
152
157
165-158
151
RTL8169
Transmit Data: In GMII mode, TxD[7:0] is a bundle of eight data
signals, representing a data byte on GMII for PHY to transmit. In MII
mode, only TxD[3:0] represent a data nibble on MII for PHY to
transmit. TxD[7:0] or TxD[3:0] transition synchronously with respect
to GTxCLK or TxCLK.
Tx[7:0]: In TBI mode, TxD[7:0] is part of the 10-bit vector (TxD[9:0])
representing one transmission code-group.
Receive Clock(0): RxCLK: In GMII mode or MII mode, the receive
clock is a continuous clock that provides the timing reference for the
transfer of the RxDV, RxER, and RxD from PHY device. RxDV, RxER,
and RxD are sampled on the rising edge of RxCLK.
RxCLK0: In TBI mode, the 62.5MHz receive clock is a continuous
clock and provides timing reference for the RTL8169 to latch
odd-numbered receive code-groups from PHY device.
Receive Clock1: RxCLK1: In TBI mode, the 62.5MHz receive clock is
a continuous clock and provides timing reference for the RTL8169 to
latch even-numbered receive code-groups from PHY device.
Receive Coding Error: In GMII or MII mode, this pin is asserted
synchronously with respect to RxCLK, to indicate that the PHY device
detected a symbol that is not part of the valid data or delimiter set
somewhere in the frame being received. The RxER may be asserted for
one or more clock cycles.
Rx[9]: In TBI mode, Rx[9] is the MSB of the 10-bit vector representing
one receive code-group. Rx[0] is the first bit received, and Rx[9] is the
last bit received.
Receive Data Valid: In GMII or MII mode, this input pin is asserted
synchronously with respect to RxCLK, to indicate that the PHY is
presenting recovered, decoded, and valid data to the RTL8169. RxDV
remains asserted while valid data is being presented by the PHY.
Rx[8]: In TBI mode, Rx[8] is a bit of the 10-bit vector representing one
receive code-group. Rx[0] is the first bit received, and Rx[9] is the last
bit received.
Receive Data: In GMII mode, RxD[7:0] is a bundle of eight data
signals, representing a data byte transmitted from PHY to the RTL8169
on GMII. In MII mode, only RxD[3:0] represent a data nibble
transmitted from PHY to the RTL8169 on MII. RxD[7:0] or RxD[3:0]
transition synchronously with respect to RxCLK.
Rx[7:0]: In TBI mode, RxD[7:0] is part of the 10-bit vector (RxD[9:0])
representing one receive code-group.
Collision Detected: In GMII or MII mode, this input pin is asserted
high by PHY to indicate the detection of a collision on the twisted pair
medium, and remains asserted while the collision condition persists. In
full duplex mode, this pin’s status is ignored by the RTL8169. The COL
transitions asynchronously with respect to RxCLK, GTxCLK, or
TxCLK.
In TBI mode, this pin’s status is ignored by the RTL8169.
2002/03/27
11
Rev.1.21
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet RTL8169.PDF ] | |
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