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PDF 29F32G08C Data sheet ( Hoja de datos )

Número de pieza 29F32G08C
Descripción NAND Flash Memory
Fabricantes Micron 
Logotipo Micron Logotipo

29F32G08C image


1. 29F32G08C - NAND Flash Memory






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No Preview Available ! 29F32G08C Hoja de datos, Descripción, Manual

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Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Features
NAND Flash Memory
MT29F32G08CBABA, MT29F64G08C[E/F]ABA, MT29F128G08C[J/K/M]ABA,
MT29F256G08CUABA, MT29F32G08CBABB, MT29F32G08CBCBB,
MT29F64G08CFABB, MT29F64G08CECBB, MT29F128G08CJABB,
MT29F128G08C[K/M]CBB, MT29F256G08CUCBB
Features
Open NAND Flash Interface (ONFI) 2.1-compliant1
Multiple-level cell (MLC) technology
Organization
Page size x8: 4320 bytes (4096 + 224 bytes)
Block size: 256 pages (1024K + 56K bytes)
Plane size: 2 planes x 2048 blocks per plane
Device size: 32Gb: 4096 blocks;
64Gb: 8192 blocks;
128Gb: 16,384 blocks;
256Gb: 32,768 blocks
Synchronous I/O performance
Up to synchronous timing mode 4
Clock rate: 12ns (DDR)
Read/write throughput per pin: 166 MT/s
Asynchronous I/O performance
Up to asynchronous timing mode 4
tRC/tWC: 25ns (MIN)
Array performance
Read page: 50µs (MAX)
Program page: 900µs (TYP)
Erase block: 3ms (TYP)
Operating Voltage Range
VCC: 2.7–3.6V
VCCQ: 1.7–1.95V, 2.7–3.6V
Command set: ONFI NAND Flash Protocol
Advanced Command Set
Program cache
Read cache sequential
Read cache random
One-time programmable (OTP) mode
Multi-plane commands
Multi-LUN operations
Read unique ID
Copyback
First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 108).
RESET (FFh) required as first command after power-
on
Operation status byte provides software method for
detecting
Operation completion
Pass/fail condition
Write-protect status
Data strobe (DQS) signals provide a hardware meth-
od for synchronizing data DQ in the synchronous
interface
Copyback operations supported within the plane
from which data is read
Quality and reliability
Data retention: 10 years
Endurance: 5000 PROGRAM/ERASE cycles
Operating temperature:
Commercial: 0°C to +70°C
Industrial (IT): –40ºC to +85ºC
Package
52-pad LGA
48-pin TSOP
100-ball BGA
Note: 1. The ONFI 2.1 specification is available at
www.onfi.org.
PDF: 09005aef836c9ded
Rev. F 12/09 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Datasheet pdf - http://www.DataSheet4U.net/

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29F32G08C pdf
wwww..DDaattaaSShheeeet4t.Uco.n.kert
Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions ............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 26
Table 3: Asynchronous Interface Mode Selection ........................................................................................... 27
Table 4: Synchronous Interface Mode Selection ............................................................................................. 37
Table 5: Command Set .................................................................................................................................. 48
Table 6: Read ID Parameters for Address 00h ................................................................................................. 53
Table 7: Read ID Parameters for Address 20h .................................................................................................. 53
Table 8: Feature Address Definitions .............................................................................................................. 54
Table 9: Feature Address 01h: Timing Mode ................................................................................................... 56
Table 10: Feature Addresses 10h and 80h: Programmable Output Drive Strength ............................................. 56
Table 11: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ..................................................... 57
Table 12: Feature Addresses 90h: Array Operation Mode ................................................................................. 57
Table 13: Parameter Page Data Structure ....................................................................................................... 60
Table 14: Status Register Definition ............................................................................................................... 72
Table 15: OTP Area Details ........................................................................................................................... 103
Table 16: Error Management Details ............................................................................................................. 108
Table 17: Output Drive Strength Test Conditions (VCCQ = 1.7–1.95V) .............................................................. 109
Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) .......................................................... 109
Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 110
Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 110
Table 21: Pull-Up and Pull-Down Output Impedance Mismatch .................................................................... 111
Table 22: Overshoot/Undershoot Parameters ................................................................................................ 112
Table 23: Test Conditions for Input Slew Rate ................................................................................................ 113
Table 24: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 113
Table 25: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 113
Table 26: Test Conditions for Output Slew Rate ............................................................................................. 114
Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) .............................................................................................. 114
Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 114
Table 29: Absolute Maximum Ratings by Device ............................................................................................ 115
Table 30: Recommended Operating Conditions ............................................................................................ 115
Table 31: Valid Blocks per LUN ..................................................................................................................... 115
Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 116
Table 33: Capacitance: 48-Pin TSOP Package ................................................................................................ 116
Table 34: Capacitance: 52-Pad LGA Package .................................................................................................. 116
Table 35: Test Conditions ............................................................................................................................. 117
Table 36: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 117
Table 37: DC Characteristics and Operating Conditions (Synchronous Interface) ........................................... 118
Table 38: DC Characteristics and Operating Conditions (3.3V VCCQ) ............................................................... 118
Table 39: DC Characteristics and Operating Conditions (1.8V VCCQ) ............................................................... 119
Table 40: AC Characteristics: Asynchronous Command, Address, and Data .................................................... 119
Table 41: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 121
Table 42: Array Characteristics ..................................................................................................................... 124
PDF: 09005aef836c9ded
Rev. F 12/09 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/

5 Page





29F32G08C arduino
wwww..DDaattaaSShheeeet4t.Uco.n.kert
Micron Confidential and Proprietary
32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync Async
x8 x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Async
x8
Sync
x8
48
47
DNU/VSSQ2 DNU/VSSQ2
NC NC
46 NC
NC
45 NC
NC
44 DQ7 DQ7
43 DQ6 DQ6
42 DQ5 DQ5
41 DQ4 DQ4
40 NC
NC
39 DNU/VCCQ2 DNU/VCCQ2
38 DNU DNU
37 VCC
VCC
36 VSS
VSS
35 DNU DQS
34
33
DNU/VCCQ2 DNU/VCCQ2
NC NC
32 DQ3 DQ3
31 DQ2 DQ2
30 DQ1 DQ1
29 DQ0 DQ0
28 NC
NC
27 NC
NC
26 DNU DNU
25 DNU/VSSQ2 DNU/VSSQ2
Notes:
1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other
configurations.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.1. If not supplying VCCQ or
VSSQ to these pins, do not use them.
PDF: 09005aef836c9ded
Rev. F 12/09 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2008 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/

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