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PDF K9MDG08U5D Data sheet ( Hoja de datos )

Número de pieza K9MDG08U5D
Descripción 4G x 8 Bit/ 8G x 8 Bit/ 16G x 8 Bit NAND Flash Memory
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K9HCG08U1D K9PDG08U5D
K9LBG08U0D K9MDG08U5D
Preliminary
FLASH MEMORY
K9XXG08UXD
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
Samsung Confidential
1
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K9MDG08U5D pdf
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K9HCG08U1D K9PDG08U5D
K9LBG08U0D K9MDG08U5D
Preliminary
FLASH MEMORY
PIN CONFIGURATION (TSOP1)
K9HCG08U1D-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48 N.C
47 N.C
46 N.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 N.C
37 Vcc
36 Vss
35 N.C
34 N.C
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 N.C
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220AF
Unit :mm/Inch
20.00±0.20
0.787±0.008
#1 #48
#24
0~8°
0.45~0.75
0.018~0.030
18.40±0.10
0.724±0.004
5
#25
1.00±0.05
0.039±0.002
01..02407MAX
0.02
0.002
MIN
(
0.50
0.020
)
Samsung Confidential
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K9MDG08U5D arduino
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K9HCG08U1D K9PDG08U5D
K9LBG08U0D K9MDG08U5D
Preliminary
FLASH MEMORY
Product Introduction
NAND Flash Memory has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system
upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through
I/O's by bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address
Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus
cycle. For example, Reset Command, Status Read Command, etc. require just one cycle bus. Some other commands, like page read
and block erase and page program, require two cycles: one cycle for setup and the other cycle for execution.. Page Read and Page
Program need the same five address cycles following the required command input. In Block Erase operation, however, only the three
row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1
defines the specific commands of the K9LBG08U0D.
Table 1. Command Sets
Function
Read
Read for Copy Back
Cache Read
Read Start for Last Page Cache Read
Page Program
Cache Program
Copy-Back Program
Block Erase
Random Data Input(1)
Random Data Output(1)
Two-Plane Read (3)
Two-Plane Read for Copy-Back(3)
Two-Plane Random Data Output (1) (3)
Two-Plane Cache Read(3)
Two-Plane Page Program(2)
Two-Plane Copy-Back Program(2)
Two-Plane Cache Program(2)
Two-Plane Block Erase
Read ID
Read Status
Chip1 Status
Chip2 Status
Reset
1st Set
00h
00h
31h
3Fh
80h
80h
85h
60h
85h
05h
60h----60h
60h----60h
00h----05h
60h----60h
80h----11h
85h----11h
80h----11h
60h----60h
90h
70h
F1h
F2h
FFh
2nd Set
30h
35h
-
-
10h
15h
10h
D0h
-
E0h
30h
35h
E0h
33h
81h----10h
81h----10h
81h----15h
D0h
-
-
-
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 80h/81h/85h is prohibited except 70h/F1h/F2h and FFh.
3. Two-Plane Random Data out must be used after Two-Plane Read or Two-Plane Cache Read operation
4. Interleave-operation between two chips is allowed.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
O
O
O
O
Samsung Confidential
11
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