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PDF D6376 Data sheet ( Hoja de datos )

Número de pieza D6376
Descripción UPD6376
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6376
AUDIO 2-CHANNEL 16-BIT D/A CONVERTER
The µPD6376 is an audio 2-channel 16-bit D/A converter.
The µPD6376 has low sound quality deterioration by employing the resistor string configuration and 0-point offset,
and low power consumption by using the CMOS process. It operates on a single 5-V power supply, and it is pin-
compatible with the µPD6372 when Pin 1 is low level or open.
FEATURES
• Single 5-V power supply
• CMOS structure
• On-chip output operational amplifier circuit
• On-chip 0-point offset circuit
• Resistor string configuration
• 8 fS (2 ch × 400 kHz) supported
• On-chip 2-channel DAC
• L-R in-phase output
ORDERING INFORMATION
Part Number
µPD6376GS
Package
16-pin plastic SOP (300 mil)
The information in this document is subject to change without notice.
Document No. S12799EJ5V0DS00 (5th edition)
(Previous No. IC-2531)
Date Published December 1997 N
Printed in Japan
The mark shows major revised points.
©
1991
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D6376 pdf
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µPD6376
2. INPUT SIGNAL FORMAT
• Input data must be input as 2’s complement, MSB first.
2’s complement is a method of expressing both positive numbers and negative numbers as binary numbers. See
the table below.
(MSB)
0111
0111
2’s Complement
1111
1111
1111
1111
Decimal Number
(LSB)
1111
+32767
1110
+32766
L.OUT, R.OUT Pin Voltage TYP. (V)
(Reference Values)Note
2.6
0000
0000
1111
0000
0000
1111
0000
0000
1111
0001
0000
1111
+1
0
–1
1.6
1000
1000
0000
0000
0000
0000
0001
0000
–32767
–32768
0.6
Note When A.VDD = 5.0 V
Values differ depending on IC fabrication variations, supply voltage fluctuations, and ambient temperature.
• Synchronize the (SI, LSI, RSI) data bit delimitations and the LRCK, WDCK reverse timing to the falling edge of
CLK.
• CLK requires the input of 16 clocks between sample data (16 bits). Also, make the time interval for 1 bit the same
as 1 clock cycle.
5
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D6376 arduino
TIMING CHART 2
• When Pin 1 is High (parallel input)
4.5 clocks
CLK
LSB
LSI 16
LSB
RSI 16
WDCK
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
MSB
N
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
N
L.OUT
N–1
R.OUT
N–1
CLK
SI
Analog output update
tSCK
tSCK
tDC tCD
CLK
WDCK
tDC
MSB
1 2 3 4 5 6 7 8 9 10 11
MSB
1 2 3 4 5 6 7 8 9 10 11
N+1
N
N
tCD

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