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PDF QS5930T Data sheet ( Hoja de datos )

Número de pieza QS5930T
Descripción LOW SKEW CMOS PLL CLOCK DRIVER
Fabricantes Integrated Device Technology 
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QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
QS5930T
FEATURES:
• 5V operation
• Q/2 output, 5 Q outputs
• Useful for Pentium, PowerPC, and PCI systems
• Internal loop filter RC network
• Low noise TTL level outputs
• <250ps rising edge output skew
• Balanced drive outputs ±24mA
• PLL bypass feature for low frequency testing
• Internal VCO/2 option for wider frequency range
• Outputs tri-state and reset while OE/RST is low
• ESD > 2000V
• Latch up > -300mA
• Available in QSOP package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The QS5930T Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q0–Q4, Q/2. Careful layout and design ensure < 250ps
skew between the Q0–Q4, and Q/2 outputs. The QS5930T includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5930T is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe sys-
tems. Several can be used in parallel or scattered throughout a sys-
tem for guaranteed low skew, system-wide clock distribution networks.
In the QSOP package, the QS5930T clock driver represents the best
value in small form factor, high-performance clock management prod-
ucts.
For more information on PLL clock driver products, see Application
Note AN-227.
SYNC
O E /R S T
FEEDBACK
PH ASE
DETECTOR
LOOP
FILTER
VCO
PLL_EN
FREQ_SEL
01
1 /2 0
RD
Q
RD
Q
RD
Q
RD
Q
RD
Q
RD
QQ
Q/2 Q4 Q3
INDUSTRIAL TEMPERATURE RANGE
c 2000 Integrated Device Technology, Inc.
1
Q2
Q1 Q0
SEPTEMBER 2000
DSC-5849
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QS5930T pdf
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QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
AC TEST LOADS AND WAVEFORMS
OUTPUT
30pF
300
300
TEST CIRCUIT 1
7.0V
OUTPUT
INDUSTRIALTEMPERATURERANGE
VDD
160
68
TEST CIRCUIT 2
28pF
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5930T
provides for replication of incoming SYNC clock signals. Any manipu-
lation of that signal, such as frequency multiplying, is performed by
digital logic following the PLL (see the block diagram). The key advan-
tage of the PLL circuit is to provide an effective zero propagation delay
between the output and input signals. In fact, adding delay circuits in
the feedback path, ‘propagation delay’ can even be negative! A simpli-
fied schematic of the QS5930T PLL circuit is shown below:
SIMPLIFIED DIAGRAM OF QS5930T FEEDBACK
Q Q/2
INP U T
PHASE
DETECTOR
V C O /2
/2
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back,
it will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system. In most applications, the output
will optimally have zero phase shift with respect to the input. In fact, the
internal loop filter on the QS5930T typically provides within 150ps of
phase shift between input and output.
If the user wishes to vary the phase difference (typically to compen-
sate for backplane delays), this is most easily accomplished by adding
delay circuits to the feedback path. The respective output used for
feedback will be advanced by the amount of delay in the feedback
path. All other outputs will retain their proper relationships to that output.
5
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