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PDF OS8104 Data sheet ( Hoja de datos )

Número de pieza OS8104
Descripción Multimedia and Control Networking Technology
Fabricantes Oasis SiliconSystems　
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No Preview Available ! OS8104 Hoja de datos, Descripción, Manual

MOST®
Media Oriented Systems Transport
Multimedia and Control
Networking Technology
OS8104
MOST Network Transceiver
Final Product Data Sheet
DS8104FP4
Jan. 2003
© Copyright 1997-2003 Oasis SiliconSystems

1 page




OS8104 pdf
OS8104
TABLE OF CONTENTS
LIST OF FIGURES ....................................................................................................... 10
LIST OF TABLES ......................................................................................................... 12
1 INTRODUCTION ....................................................................................................... 15
2 FUNCTIONAL DESCRIPTION .................................................................................. 17
2.1 Network Interface & Compatibility .................................................................................................. 17
2.2 On-Chip Network Management ...................................................................................................... 18
2.2.1 Channel Allocation ................................................................................................................. 19
2.2.2 Physical Position Sensing ...................................................................................................... 19
2.2.3 Network Delay Detection ........................................................................................................19
2.2.4 Node Alive Supervision .......................................................................................................... 19
2.3 On-Chip Power Management ......................................................................................................... 20
2.4 Data Transfer Methods ................................................................................................................... 20
2.5 Bandwidth .......................................................................................................................................21
2.5.1 Control Messaging ................................................................................................................. 21
2.5.2 Synchronous (Stream) Data ................................................................................................... 21
2.5.3 Asynchronous (Packet) Data .................................................................................................22
2.6 MOST NetServices API .................................................................................................................. 24
3 MAIN FUNCTIONAL BLOCKS ................................................................................. 25
4 CONFIGURATION ..................................................................................................... 27
5 CONTROL PORT IN SERIAL MODE ........................................................................ 29
5.1 I2C Mode ........................................................................................................................................ 30
5.1.1 Writing to the Control Port ...................................................................................................... 31
5.1.2 Reading from the Control Port ............................................................................................... 32
5.2 SPI Mode ........................................................................................................................................ 33
5.2.1 Writing to the Control Port ...................................................................................................... 33
5.2.2 Reading from the Control Port ............................................................................................... 34
6 NETWORK INTERFACE ........................................................................................... 35
6.1 MOST Frame Structure .................................................................................................................. 35
6.2 Network Configuration ....................................................................................................................36
6.2.1 bXCR (Transceiver Control Register) .................................................................................... 37
6.2.2 bXSR (Transceiver Status Register) ...................................................................................... 38
6.2.3 bXSR2 (Transceiver Status Register 2) ................................................................................. 39
6.2.4 Transceiver Error Events ....................................................................................................... 39
6.2.5 bSBC (Synchronous Bandwidth Control Register) ................................................................. 40
6.2.6 bNDR (Node Delay Register) .................................................................................................41
6.2.7 bNPR (Node Position Register) ............................................................................................. 41
6.2.8 bMPR (Maximum Position Register) ...................................................................................... 42
6.2.9 bMDR (Maximum Delay Register) ......................................................................................... 42
6.2.10 Network Registers After Lock ............................................................................................... 42
7 SOURCE PORTS IN SERIAL MODE ........................................................................ 43
7.1 Serial Source Port Interface ........................................................................................................... 44
7.2 Source Port Configuration (Serial) .................................................................................................46
7.2.1 bSDC1 (Source Data Control Register 1) ..............................................................................46
Final Product Data Sheet
© Copyright 1997-2003 Oasis SiliconSystems
DS8104FP4
Page 5

5 Page





OS8104 arduino
OS8104
Figure 9-2: Standard Application for VREF and FLT Pins .......................................................................91
Figure 9-3: Crystal Oscillator Input........................................................................................................... 92
Figure 11-1: Multiple-Interrupt Events ........................................................................................................96
Figure 12-1: Routing Engine ......................................................................................................................98
Figure 12-2: Routing Process Example ..................................................................................................... 99
Figure 12-3: Source Port Serial Format: Table vs. SRn Example............................................................ 104
Figure 12-4: Source Port Output Routing Example (MRT Locations) ...................................................... 105
Figure 12-5: MRT Power-up Defaults ......................................................................................................109
Figure 13-1: Control Message Types ....................................................................................................... 111
Figure 13-2: INT and ERROR Pins Logical Schematic ............................................................................116
Figure 13-3: Control Message Reception Flow ........................................................................................121
Figure 13-4: Sending MOST Control Messages: Interrupt Service Routine ............................................ 122
Figure 13-5: Sending MOST Control Messages: Polling ......................................................................... 123
Figure 13-6: Resource Allocation Flow .................................................................................................... 128
Figure 15-1: Preparing Packet Data for Transmission ............................................................................. 140
Figure 15-2: Handling Packet Data Transfer by Polling ........................................................................... 141
Figure 15-3: Handling Packet Data Transfer via Interrupt........................................................................ 142
Figure 16-1: Starting up - Initial Flow ....................................................................................................... 144
Figure 16-2: Starting up - Timing-Master Configuration ........................................................................... 145
Figure 16-3: Starting up - Timing-Slave Configuration ............................................................................. 146
Figure 17-1: Stand-Alone Mode: Write Flow ............................................................................................ 151
Figure 17-2: Stand-Alone Mode: Read Flow............................................................................................ 154
Figure 18-1: RX Pulse-Width Distortion ................................................................................................... 158
Figure 18-2: RX Jitter ............................................................................................................................... 158
Figure 18-3: Reset Pulse Width ............................................................................................................... 159
Figure 18-4: Parallel Read Operation ......................................................................................................161
Figure 18-5: Parallel Write Operation....................................................................................................... 161
Figure 18-6: Source Port External Timing ................................................................................................ 162
Figure 18-7: Source Port Internal Timing ................................................................................................. 163
Figure 18-8: Control Port Timing in SPI Mode ......................................................................................... 164
Figure 18-9: Control Port Timing in I2C mode. ......................................................................................... 165
Figure 19-1: Pin Equivalent for Analog Input Pins and Output Pins (A) ................................................... 173
Figure 19-2: Pin Equivalent for Digital Input Pin (DIN).............................................................................. 173
Figure 19-3: Pin Equivalent for Digital Output Pin (DOUT)........................................................................ 173
Figure 19-4: Pin Equivalent for Digital Output Pin with Tri-State (DOUTZ)................................................ 173
Figure 19-5: Pin Equivalent for Bi-directional Digital Output Pin (DI/O) .................................................... 174
Figure 19-6: Pin Equivalent for Digital Open-Drain Output Pin with Internal Pull-up (DOODP) .................174
Figure 19-7: Pin Equivalent for Bi-directional Digital and Configurable Pin (DI/O+CONF).......................... 174
Figure 19-8: Pin Equivalent for Bi-directional Digital Pin with Open-Drain (DI/O+OD) ...............................175
Figure 19-9: Pin Equivalent for Digital Open-Drain Output Pin (DOOD).................................................... 175
Figure 19-10:Pinout Block Diagram.......................................................................................................... 176
Figure 19-11:Pinout .................................................................................................................................. 177
Figure 19-12:Package Outline..................................................................................................................178
Figure 20-1: EMI-Reducing Circuits ......................................................................................................... 179
Figure 20-2: Typical Power Supply Connection Diagram ........................................................................ 181
Figure 20-3: Typical Schematic................................................................................................................ 182
Figure 20-4: Typical Layout...................................................................................................................... 183
Figure 20-5: Typical Application — Source Ports in Serial Mode, Control Port in I2C Mode ...................184
Figure 20-6: Typical Application — Source Ports in Serial Mode, Control Port in SPI Mode...................185
Figure 20-7: Typical Application — Source Ports in Parallel, Control Port in I2C Mode........................... 186
Figure 20-8: Typical Application — Source Port and Control Port in Parallel Mode ................................ 187
Figure 20-9: Typical Application — Stand-Alone Mode ........................................................................... 188
Final Product Data Sheet
© Copyright 1997-2003 Oasis SiliconSystems
DS8104FP4
Page 11

11 Page







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