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PDF ICS9LP525-2 Data sheet ( Hoja de datos )

Número de pieza ICS9LP525-2
Descripción 56-pin CK505
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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DATASHEET
56-pin CK505 for Intel Desktop Systems
ICS9LP525-2
Recommended Application:
CK505 clock, 56-pin Intel Yellow Cover part
Output Features:
• 2 - CPU differential low power push-pull pairs
• 7- SRC differential low power push-pull pairs
• 1 - CPU/SRC selectable differential low power push-pull pair
• 1 - SRC/DOT selectable differential low power push-pull pair
• 5 - PCI, 33MHz
• 1 - PCI_F, 33MHz free running
• 1 - USB, 48MHz
• 1 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/- 100ppm frequency accuracy on all outputs
• SRC are PCIe Gen2 compliant
Features/Benefits:
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Selectable SRC differential push-pull pair/two single
ended outputs
Table 1: CPU Frequency Select Table
FSLC2
B0b7
0
0
0
0
1
1
1
1
FSLB1
B0b6
0
0
1
1
0
0
1
1
FSLA1
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC PCI REF USB DOT
MHz MHz MHz MHz MHz
100.00 33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
IDT® PC MAIN CLOCK
PCI0/CR#_A 1
56 SCLK
VDDPCI 2
55 SDATA
PCI1/CR#_B 3
PCI2/TME 4
PCI3/CFG0 5
PCI4/SRC5_EN 6
PCI_F5/ITP_EN 7
GNDPCI 8
VDD48 9
USB_48MHz/FSLA 10
GND48 11
VDD96_IO 12
DOTT_96/SRCT0 13
DOTC_96/SRCC0 14
GND 15
VDD 16
SRCT1/SE1 17
SRCC1/SE2 18
GND 19
VDDPLL3_IO 20
SRCT2/SATAT 21
SRCC2/SATAC 22
GNDSRC 23
SRCT3/CR#_C 24
SRCC3/CR#_D 25
VDDSRC_IO 26
SRCT4 27
SRCC4 28
54 REF0/FSLC/TEST_SEL
53 VDDREF
52 X1
51 X2
50 GNDREF
49 FSLB/TEST_MODE
48 CK_PWRGD/PD#
47 VDDCPU
46 CPUT0
45 CPUC0
44 GNDCPU
43 CPUT1_F
42 CPUC1_F
41 VDDCPU_IO
40 VOUT
39 CPUT2_ITP/SRCT8
38 CPUC2_ITP/SRCC8
37 VDDSRC_IO
36 SRCT7/CR#_F
35 SRCC7/CR#_E
34 GNDSRC
33 SRCT6
32 SRCC6
31 VDDSRC
30 PCI_STOP#/SRCT5
29 CPU_STOP#/SRCC5
56-SSOP & TSSOP
1
1397—11/08/10

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ICS9LP525-2 pdf
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ICS9LP525-2
PC MAIN CLOCK
External Pass Transistor Connection for Desktop Applications
ICS9LP525-2
VDDCPU_IO, Pin 41
3.3V
-
+
Vref
VOUT
PIN 40
R=33
C=100pF
3.3V
R=15
2N3904
VD D_IO
0.8V N OM .
C >= 40uF
CPU_IO Decoupling
Network
96_IO Decoupling
Network
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
VDDSRC_IO Pin 37, 26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
IDTTM/ICSTM PC MAIN CLOCK
5
1397—11/08/10

5 Page





ICS9LP525-2 arduino
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ICS9LP525-2
PC MAIN CLOCK
Table 4: Device ID table
B8b7 B8b6 B8b5
000
B8b4
0
Comment
56 pin TSSOP
Table 5: Slew Rate Selection Table
Bit 1 Bit 0
Slew Rate
00
HI-Z
0 1 0.7X (1.4V/ns)
1 0 0.8X (1.6 V/ns)
1 1 1X (2.0 V/ns)
Table 6. PCI3 Configuration Table
Note: 2 bits are needed since
CFG0 is tri-level input
SRC_Main_SE
PCI3/CFG0 PCI2/TME PCI3_CFG1 PCI3_CFG0
L
HW Strap HW Strap (Byte 11, bit 7) (Byte 11, bit 6) (Byte 0, bit 2) Config Mode
Low 0 or 1
0
0 0 0 = Default
Mid 0 or 1
0
1 11
High
TME=0
1
0 12
High
TME=1
1
1 13
Table 7. PLL Modes for PCI3 Configurations
Config
PLL1
PLL2
Mode
Outputs
SSC
Outputs
SSC
CPU/SRC/
0 = Default
PCI
Down
USB
NA
1
CPU
Down
USB
NA
2
CPU
Center
USB
NA
3
CPU
Center
USB/LAN25
NA
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
PLL3
Outputs
SSC
-
SRC/PCI
SRC/PCI
SRC/PCI
-
Down
Down
Down
SRC1 PLL Source
PLL1
(Table 2
100MHz applies)
100MHz
PLL3
100MHz
PLL3
25MHz SE PLL2*
Table 8. ME Clock Selection Table
PCIF5/
ITP_EN iAMT_EN CPU2_AMT_EN CPU1_AMT_EN
Description
x1
0
0
Reserved
x1
0
1 Default, CPU1 = iAMT Clock
11
1
0 CPU2 = iAMT Clock
11
1
1 CPU1 and CPU2 both run in iAMT mode
IDTTM/ICSTM PC MAIN CLOCK
11
1397—11/08/10

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