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PDF F81865 Data sheet ( Hoja de datos )
| Número de pieza | F81865 | |
| Descripción | Super IO | |
| Fabricantes | Feature Integration Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de F81865 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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F81865
F81865
Super IO with 6 UARTs
Release Date: May, 2010
Version: V0.28P
May, 2010
V0.28P
1 page  
www.DataSheet4U.net
F81865
1. General Description
The F81865 is the featured IO chip for Industrial PC system. Equipped with one IEEE
1284 parallel port, 6 UART ports with 9-bit protocol, KBC, Serial Peripheral Interface (SPI),
SIR and one FDC. The F81865 integrated with hardware monitor, 7 sets of voltage sensor, 2
sets of creative auto-controlling fans and 2 temperature sensor pins for the accurate dual
current type temperature measurement for CPU thermal diode or external transistors
2N3906.
The F81865 provides flexible features for multi-directional application. For instance,
supports 53 GPIO pins, IRQ sharing function designed in UART feature for particular usage
and accurate current mode H/W monitor will be worth in measurement of temperature, the
F81865 also integrated SPI interface. The SPI interface is for BIOS usage including bridge
function. Others, the F81865 supports newest Intel PECI interfaces for new generational
CPU temperature use. Furthermore, F81865 provides independent RTC function.
These features as above description will help you more and improve product value.
Finally, the F81865 is powered by 3.3V voltage, with the LPC interface in the package of
128-PQFP.
2. Feature List
General Functions
¾ Comply with LPC 1.1
¾ Support ACPI 3.0
¾ Provides one FDC, KBC and Parallel Port
¾ Provide 6 fully functional UART and 1 SIR
¾ 9-bit Protocol for UARTs
¾ Support IRQ Sharing function.
¾ H/W monitor functions
¾ SPI interface for BIOS
¾ RTC function
¾ Support PECI 1.0 interface
¾ 53 GPIO Pins for flexible application
¾ 24/48 MHz clock input
¾ Packaged in 128-PQFP and powered by 3.3VCC
5 May, 2010
V0.28P
5 Page 
www.DataSheet4U.net
6.2 LPC Interface
Pin No.
23
24
25
26
Pin Name
LRESET#
LDRQ#
SERIRQ
LFRAME#
Type
INst,5v
O12
I/O24t
INst
27-30
32
33
LAD[0:3]
PCICLK
CLKIN
I/O24t
INst
INst
F81865
PWR
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Description
Reset signal. It can connect to PCIRST# signal on the
host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a
broken cycle.
These signal lines communicate address, control, and
data information over the LPC bus between a host and
a peripheral.
33MHz PCI clock input.
System clock input. According to the input frequency
24/48MHz.
6.3 FDC
Pin No.
Pin Name
DENSEL#
9 GPIO50
RTS6_2#
MOA#
10 GPIO51
SIN6_2
IRRX_2
DRVA#
11 GPIO52
SOUT6_2
IRTX_2
WDATA#
12 GPIO53
DCD6#
Type
OD14
I/OOD14
O14
OD14
I/OOD14
INt,5v
INt,5v
OD14
I/OOD14
O14
O14
OD14
I/OOD14
INt,5v
PWR
VCC
VCC
VCC
VCC
Description
Drive Density Select.
Set to 1 – High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
General Purpose IO.
UART Request To Send. An active low signal informs
the modem or data set that the controller is ready to
send data.
Motor A On. When set to 0, this pin enables disk drive
0. This is an open drain output.
General Purpose IO.
UART Serial Input. Used to receive serial data
through the communication link.
Infrared Receiver input.
Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
General Purpose IO.
UART Serial Output. Used to transmit serial data out
to the communication link.
Infrared Transmitter Output.
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD. An
open drain output.
General Purpose IO.
Data Carrier Detect. An active low signal indicates
the modem or data set has detected a data carrier.
11 May, 2010
V0.28P
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet F81865.PDF ] | |
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