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PDF PE12016G Data sheet ( Hoja de datos )

Número de pieza PE12016G
Descripción (PE12016G / PE12024G) Incremental Encoder
Fabricantes Productivity Engineering 
Logotipo Productivity Engineering Logotipo



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PE12016G / PE12024G
December 15, 2005 Version 1.7
Incremental Encoder
Features:
Functional and pincompatible with obsolete
TI CF32007NW/NT / THCT12016 /
THCT 12024 / LS2000
5 V and 3.3 V Operation
0.6u CMOS Process
Direction discriminator
Pulse width measurement
Frequency measurement
Cascadable (PE12016G only)
TTL compatible
8 Bit parallel tristateable Bus
Simple read & write procedure
High speed 20 MHz clock operation
PE12016G ONLY: 1:1 Replacement for
LS2000AN
PE12024G ONLY: 24-Bit resolution,
separate UA0 counter reset
WEEE & RoHS Compliant according
DIRECTIVE 2002/95/EC
(Green Package Material)
PE12016G
PDIP28-600 Mil
1
CS
28
VCC
RD UP
D0 DOWN
D1 WE
D2 RESET
D3 A0
GND
CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
BORROW
M2
CARRY READY
GND KLI-KLO
14 15
PE12024G
PDIP24-300 Mil
1 24
CS VCC
RD UA0
D0 A1
D1 WE
D2 RESET
D3 A0
GND CLK
D4 UA2
D5 UA1
D6 M0
D7 M1
GND
12
M2
13
Description:
The PE12016G/12024G INCREMENTAL
ENCODER INTERFACE can independently
determine the direction or displacement of a
mechanical device or axis based on two input
signals from transducers in quadrature.
Alternatively, it can measure a pulse width using
a known clock rate, or a frequency, by counting
input pulses over a
known time interval. It includes one 16-bit or 24-
bit counter which may also be used separately
(PE12016G only). The PE12016G may be
cascaded to provide accuracy greater than 16-
bits. Both devices are designed for use in many
microprocessor-based systems.
December 15, 2005 (Version 1.7)
Seite 1 / 25
PE12016G/24G

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PE12016G pdf
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PE12016G / PE12024G
Incremental Encoder
December 15, 2005 Version 1.7
Table 1: PE12016G/12024G Operation Modes
Detailed Information about the different Modes:
Mode 0: 16-Bit Up/Down Counter Mode
In this mode the PE12016G may be used as a
fast 16-bit up/down counter with cascade
capability. This is operated using the /UP and
/DOWN inputs.
The states of the counter outputs are transferred
to a 16-bit latch. The contents of this 16-bit latch
are multiplexed on a 8-bit parallel data bus
(D0…D7) and enabled using /RD and /CS.
/A0 is the control input for the byte multiplexer. A
high level at this input transfers the least
significant byte to the data outputs; and a low
level transfers the most significant byte.
The up/down counters are loaded in individual 8-
bit bytes by the /WR and /CS signals, with the
byte selected by the /A0 input. The counter may
be cleared using the /RESET signals (which
clears both counter and control logic), or
individually, using Ua0 signal (PE12024G) only.
Cascading to n-bits is possible using inputs /UP
and /DOWN, outputs /BORROW, /CARRY and
the input-outputs /KLI-KLO (PE12016G only).
NOTE: The PE12024G cannot be used in Mode 0 since /UP and /DOWN inputs are not available.
To read or load the 24-bit (PE12024G only) in all
modes, /CS, /RD or /WR, /A0 and /A1 are used
to perform the Read or Write operation. The
operation should always start with the LSB
(/A0=/A1=HIGH), followed by the LSB+1
(/A0=LOW, /A1=HIGH) and then the MSB
(/A0=HIGH, /A1=LOW).
/A0 /A1 BYTE REMARKS ON D0-D7
H H LSB PE12016G only
L H LSB+1
H L MSB
PE12024G
L L ALL X
extensions
Table 2: PE12024G Address Select
December 15, 2005 (Version 1.7)
Seite 5 / 25
PE12016G/24G

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PE12016G arduino
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December 15, 2005 Version 1.7
Pin Description
Pin Name Pin Number
PDIP28 PDIP24
PE12016G PE12024G
/CS 1 1
/RD 2 2
D0
D1
D2
D3
D4
D5
D6
D7
/BORROW
3
4
5
6
8
9
10
11
12
3
4
5
6
8
9
10
11
-
/CARRY
13
-
/KLI-KLO
15
-
/READY
16
-
M2 17 13
M1 18 14
M0 19 15
Ua1 20 16
Ua2 21 17
PE12016G / PE12024G
Incremental Encoder
I/O Description
Input
Input
Chip Select. A low enables the device.
Read. When this and /CS are active
(low), the data from the output register
will be present on the data bus.
LSB
Input/
Output
(3-state)
Data Bus Buffer:
8-Bit bidirectional Buffer with 3-state
outputs connected to the microprocessor
system.
MSB
Output Push-pull output of the Counter
(PP) underflow signal (PE12016G only).
Output Counter overflow signal (PE12016G
(PP) only)
Input/ Cascade load input / cascade load
Output output. Open drain (OD) output with
(OD with internal 75K
Pull-up) (nom) pull-up. (PE12016G only)
Output
(PP)
When active low, the signal indicates to
the MPU that read or write may be
completed. /READY falling edge is
synchronous with CLK. The push pull
output requires no external pull-up
resistor (PE12016G only).
Input Mode Select Inputs (see Table 1)
Input
Input
Input Measuring input signals
Input
December 15, 2005 (Version 1.7)
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