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PDF K9HDG08U5A Data sheet ( Hoja de datos )
| Número de pieza | K9HDG08U5A | |
| Descripción | 32Gb A-die NAND Flash | |
| Fabricantes | Samsung | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de K9HDG08U5A (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
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Rev.1.0, May. 2010
K9GBG08U0A
K9LCG08U1A
K9HDG08U5A
32Gb A-die NAND Flash
Multi-Level-Cell (2bit/cell)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2009 Samsung Electronics Co., Ltd. All rights reserved.
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K9GBG08U0A
K9LCG08U1A K9HDG08U5A
1.0 Introduction
1.1 Product List
Part Number
K9GBG08U0A-M
K9LCG08U1A-M
K9HDG08U5A-M
Density
32Gb
64Gb
128Gb
datasheet
Rev. 1.0
FLASH MEMORY
Interface
Conventional
VccQ Range
2.7V ~ 3.6V
Vcc Range
2.7V ~ 3.6V
Organization
x8
PKG Type
52LGA
48TSOP
1.2 Features
• Voltage Supply
- Core voltage : 3.3V(2.7V ~ 3.6V)
- I/O voltage : 3.3V(2.7V~ 3.6V)
• Organization of Single die
- Memory Cell Array : 8,832 x 519K x 8bit
- Data Register : (8K + 640) x 8bit
• Automatic Program and Erase
- Page Program : (8K + 640)Byte
- Block Erase : (1M + 80K)Byte
• Page Read Operation
- Page Size : (8K + 640)Byte
- Random Read(tR) : 250μs(Average Typ.), 300μs(Average Max.)
- Serial Access : 25ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Write Cycle Time
- Program time : 1.3ms(Typ.)
- Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- ECC : 40bit/(1K+80)Byte
- Endurance & Data Retention : Please refer to the Qualification report
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
- K9GBG08U0A-MCB0/MIB0 : Pb/Halogen-Free Package
52-Pin LGA (13 x 18 / 1.00 mm pitch)
- K9LCG08U1A-MCB0/MIB0 : Pb/Halogen-Free Package
52-Pin LGA (13 x 18 / 1.00 mm pitch)
- K9HDG08U5A-MCB0/MIB0 : Pb/Halogen-Free Package
52-Pin LGA (13 x 18 / 1.00 mm pitch)
- K9GBG08U0A-SCB0/SIB : Pb/Halogen-Free Package
48-Pin TSOP (12 x 20 / 1.00 mm pitch)
- K9LCG08U0A-SCB0/SIB0 : Pb/Halogen-Free Package
48-Pin TSOP (12 x 20 / 1.00 mm pitch)
- K9HDG08U1A-SCB0/SIB0 : Pb/Halogen-Free Package
48-Pin TSOP (12 x 20 / 1.00 mm pitch)
1.3 General Description
The device is offered in 3.3V Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation
can be performed in typical 1.3ms on the 8,832-byte page and an erase operation can be performed in typical 1.5ms on a (1M+80K)byte block. Data in
the data register can be read out at Read cycle time(tRC) per byte. The I/O pins serve as the ports for address and data input/output as well as command
input. The on-chip write controller automates all program and erase functions including pulse repetition, where required, and internal verification and mar-
gining of data. Even the write-intensive systems can take advantage of the K9XXG08XXA′s extended reliability of P/E cycles which are presented in the
Qualification report by providing ECC(Error Correcting Code) with real time mapping-out algorithm. These NAND devices are an optimum solution for
large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.
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5 Page 
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K9GBG08U0A
K9LCG08U1A K9HDG08U5A
datasheet
1.9 Pin Configuration (48TSOP, QDP)
Rev. 1.0
FLASH MEMORY
K9HBG08U1A-SCB0/SIB0
Vcc
Vss
N.C
N.C
N.C
R/B2
R/B1
RE
CE1
CE2
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
Vss
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
48 Vss
47 N.C
46 N.CN.C
45 N.C
44 I/O7
43 I/O6
42 I/O5
41 I/O4
40 N.C
39 N.C
38 VccQ
37 Vcc
36 Vss
35 N.C
34 VccQ
33 N.C
32 I/O3
31 I/O2
30 I/O1
29 I/O0
28 N.C
27 N.C
26 N.C
25 Vss
1.9.1 Package Dimensions
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
48 - TSOP1 - 1220BF
(1.00)
#1 ( 0.80 Dp 0~0.05)
(1.00)
#48
1.20MAX
1.05.±0.3
(13°)
Unit :mm
(10°)
#24
18.40.±0.10
(18.80)
(19.00)
20.00.±0.20
#25
(13°)
(10°)
(R0.15)
0.02 MIN
(R0.25)
(R0.25)
(0.50)
0.45 ~ 0.75
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