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PDF ICS9LPRS545 Data sheet ( Hoja de datos )

Número de pieza ICS9LPRS545
Descripción 48-pin CK505
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No Preview Available ! ICS9LPRS545 Hoja de datos, Descripción, Manual

Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
48-pin CK505 for Intel Systems
Recommended Application:
48-pin Low Cost CK505 w/fully integrated VREG and series
resistors on differential outputs
Output Features:
• Integrated Series Resistors on differential outputs
• 2 - CPU differential push-pull pairs
• 4 - SRC differential push-pull pairs
• 1 - CPU/SRC selectable differential push-pull pair
• 1 - SRC/DOT selectable differential push-pull pair
• 1- SRC/Stop_Inputs selectable differential push-pull pair
• 1 - 25MHz SE1 output for Wake-on-Lan applications
• 3 - PCI, 33MHz
• 1 - USB, 48MHz
• 1 - REF, 14.31818MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• SRC output cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 250ps
• +/-100ppm frequency accuracy on all clocks
Features/Benefits:
• Supports spread spectrum modulation, default is 0.5%
down spread
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Not recommended for new designs.The last time
buy date for this product is 5/19/2011. Please refer
to PDN K-10-18.
Table 1: CPU Frequency Select Table
FSLC2 FSLB1 FSLA1
B0b7 B0b6 B0b5
CPU
MHz
SRC
MHz
PCI
MHz
REF
MHz
USB
MHz
0 0 0 266.66
0 0 1 133.33
0 1 0 200.00
0 1 1 166.66 100.00 33.33 14.318 48.00
1 0 0 333.33
1 0 1 100.00
1 1 0 400.00
111
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
DOT
MHz
96.00
Pin Configuration
1479A—07/28/09
PCI0/CR#_A 1
48 SCLK
VDDPCI 2
47 SDATA
PCI4/SRC5_EN 3
PCI_F5/ITP_EN 4
GNDPCI 5
VDD48 6
46 REF0/FSLC/TEST_SEL
45 VDDREF
44 X1
43 X2
USB_48MHz/FSLA 7
42 GNDREF
GND48 8
41 FSLB/TEST_MODE
VDD96_IO 9
DOT96T_LPR/SRCT0_LPR 10
DOT96C_LPR/SRCC0_LPR 11
GND 12
40 CK_PWRGD/PD#
39 VDDCPU
38 CPUT0_LPR
37 CPUC0_LPR
VDD 13
36 GNDCPU
SE1 14
35 CPUT1_LPR_F
GND 15
SRCT2_LPR/SATAT_LPR 16
SRCC2_LPR/SATAC_LPR 17
GNDSRC 18
34 CPUC1_LPR_F
33 VDDCPU_IO
32 CPUT2_ITP_LPR/SRCT8_LPR
31 CPUC2_ITP_LPR/SRCC8_LPR
SRCT3_LPR/CR#_C 19
30 VDDSRC_IO
SRCC3_LPR/CR#_D 20
29 SRCT7_LPR/CR#_F
VDDSRC_IO 21
SRCT4_LPR 22
SRCC4_LPR 23
CPU_STOP#/SRCC5_LPR 24
28 SRCC7_LPR/CR#_E
27 GNDSRC
26 VDDSRC
25 PCI_STOP#/SRCT5_LPR
48-SSOP/TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
www.DICaStareSsheerveets4tUhe.nrigehtt to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

1 page




ICS9LPRS545 pdf
Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
Absolute Maximum Ratings - DC Parameters
PARAMETER
SYMBOL
CONDITIONS
Maximum Supply Voltage
VDDxxx
Supply Voltage
Maximum Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
Maximum Input Voltage
VIH
3.3V Inputs
Minimum Input Voltage
VIL
Any Input
Storage Temperature
Ts
-
Input ESD protection
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied, nor guaranteed.
3 Maximum input voltage is not to exceed VDD
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
Differential Voltage Swing
Crossing Point Voltage
Crossing Point Variation
Maximum Output Voltage
Minimum Output Voltage
Duty Cycle
CPU[1:0] Skew
CPU[2_ITP:0] Skew
SRC[10:0] Skew
SYMBOL
tSLR
tFLR
tSLVAR
VSWING
VXABS
VXABSVAR
VHIGH
VLOW
DCYC
CPUSKEW10
CPUSKEW20
SRCSKEW
CONDITIONS
Averaging on
Averaging on
Averaging on
Averaging off
Averaging off
Averaging off
Averaging off
Averaging off
Averaging on
Differential Measurement
Differential Measurement
Differential Measurement
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
UNITS
V
V
V
V
°C
V
Notes
7
7
4,5,7
4,7
4,7
6,7
MIN MAX UNITS NOTES
2.5 4 V/ns 2, 3
2.5 4 V/ns 2, 3
20 % 1, 10
300 mV 2
300 550 mV 1,4,5
140 mV 1,4,9
1150 mV 1,7
-300 mV 1,8
45 55 % 2
100 ps 1
150 ps 1
3000
ps 1,6,11
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1Measurement taken for single ended waveform on a component test board (not in system)
2 Measurement taken from differential waveform on a component test board. (not in system)
3 Slew rate emastured through V_swing voltage range centered about differential zero
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
5 Only applies to the differential rising edge (Clock rising, Clock# falling)
6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.
7 The max voltage including overshoot.
8 The min voltage including undershoot.
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
i1n0dMuactecdhimngodauplpaltiieosn tboyrisseinttginegdCge_crraotessfo_rdeCltloactko abnedsfmalalinllegr ethdagne Vra_tCerfoosr sCalobcsko#lu. teIt is measured using a +/-75mV window centered on the average cross point where Clock rising
m11 eFeotrs PCCloIeckG#efna2llincgo.mTphliaenmt deedviaicnecsr,oSsRs Cpo3in,t4i,s6u,saenddt7o wcailllchualavtee0thpesvnooltmagineal skew.
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
Long Accuracy
ppm
Clock period
Tperiod
Absolute min/max period
Output High Voltage
Output Low Voltage
Output High Current
Tabs
VOH
VOL
IOH
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Pin to Pin Skew
Intential PCI to PCI delay
Duty Cycle
Jitter, Cycle to cycle
IOL
tSLR
tFLR
tskew
tskew
dt1
tjcyc-cyc
CONDITIONS
see Tperiod min-max values
33.33MHz output no spread
33.33MHz output spread
33.33MHz output no spread
33.33MHz output nominal/spread
IOH = -1 mA
IOL = 1 mA
V OH @MIN = 1.0 V
VOH@MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
MIN
-100
29.99700
30.08421
29.49700
29.56617
2.4
-33
30
1
1
100
45
MAX UNITS NOTES
100 ppm 1,2
30.00300 ns
2
30.23459 ns
2
30.50300 ns
2
30.58421 ns
2
V1
0.55 V 1
mA 1
-33 mA 1
mA 1
38 mA 1
4 V/ns 1
4 V/ns 1
250 ps 2
200 ps 2
55 % 2
500 ps 2
1479A—07/28/09
5

5 Page





ICS9LPRS545 arduino
Integrated
Circuit
Systems, Inc.
ICS9LPRS545
Datasheet
Byte 0 FS Readback and PLL Selection Register
Bit Pin
Name
Description
7-
6-
5-
4-
3
FSLC
FSLB
FSLA
iAMT_EN
Reserved
CPU Freq. Sel. Bit (Most Significant)
CPU Freq. Sel. Bit
CPU Freq. Sel. Bit (Least Significant)
Set via SMBus or dynamically by CK505 if detects
dynamic M1
Reserved
2-
SRC_Main_SEL
Select source for SRC Main
1-
SATA_SEL
Select source for SATA clock
Type
R
R
R
01
See Table 1 : CPU Frequency Select
Table
RW Legacy Mode
iAMT Enabled
RW
R SRC Main = PLL1 SRC Main = PLL3
RW SATA = SRC_Main SATA = PLL2
Default
Latch
Latch
Latch
0
0
0
0
0-
PD_Restore
1 = on Power Down de-assert return to last known state
0 = clear all SMBus configurations as if cold power-on
and go to latches open state
This bit is ignored and treated at '1' if device is in iAMT
mode.
RW
Configuration Not
Saved
Configuration Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin
Name
Description
7 13/14
SRC0_SEL
Select SRC0 or DOT96
6-
PLL1_SSC_SEL
Select 0.5% down or center SSC
Type
RW
RW
0
SRC0
Down spread
1
DOT96
Center spread
Default
0
0
5 Reserved
Reserved
RW
1
4 PLL3_CF3
3 PLL3_CF2
2 PLL3_CF1
1 PLL3_CF0
0 PCI_SEL
PLL3 Quick Config Bit 3
PLL3 Quick Config Bit 2
PLL3 Quick Config Bit 1
PLL3 Quick Config Bit 0
PCI_SEL
R
R 25MHz from PLL3 Quick Config
R
R
R PCI from PLL1
PCI from
SRC_MAIN
1
1
0
0
1
Byte 2 Output Enable Register
Bit Pin
Name
Description
7
REF_OE
Output enable for REF, if disabled output is tri-stated
6 USB_OE
Output enable for USB
5 PCIF5_OE
Output enable for PCI5
4 PCI4_OE
Output enable for PCI4
3 Reserved
Reserved
2 Reserved
Reserved
1 Reserved
Reserved
0 PCI0_OE
Output enable for PCI0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
Byte 3 Output Enable Register
Bit Pin
Name
7 Reserved
6 Reserved
5 Reserved
4 SRC8/ITP_OE
3 SRC7_OE
2 Reserved
1 SRC5_OE
0 SRC4_OE
Description
Reserved
Reserved
Reserved
Output enable for SRC8 or ITP
Output enable for SRC7
Reserved
Output enable for SRC5
Output enable for SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
1479A—07/28/09
11

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