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PDF STR-W6750 Data sheet ( Hoja de datos )
| Número de pieza | STR-W6750 | |
| Descripción | Off-Line Quasi-Resonant Switching Regulators | |
| Fabricantes | Allegro MicroSystems | |
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SwRitecghuinlagtors
www.DataSheet4U.net
PRODUCT
DESCRIPTION
Series STR-W6750 Off-Line
Quasi-Resonant Switching Regulators
INTRODUCTION
The Series STR-W6750 devices are hybrid integrated circuits
(HICs) with a built-in power MOSFET and a control IC
designed for quasi-resonant type switch-mode power supplies
(SMPS). In normal operation, the HIC provides high effi-
ciency and low EMI noise with bottom-skip quasi-resonant
operation during light output loads. Low power consumption
is also achieved by blocking (intermittent) oscillation during an
auto-burst mode and reduced even further in a manually
triggered (clamping an output voltage) standby mode.
The HIC is supplied in a seven-pin fully-molded TO-220-style
package with pin 2 deleted, which is suitable for downsizing
and standardizing of an SMPS by reducing external component
count and simplifying circuit design.
Features
Blocking (or intermittent) oscillation operation by reducing
output voltage in the standby mode.
In addition to the standard quasi-resonant operation, a
bottom-skip function is available for increased efficiency
from light to medium load.
Soft-start operation at start-up.
Reduced switching noise (compared to conventional PWM
hard-switching solution) with a step-drive function.
Built-in avalanche-energy-guaranteed power MOSFET (to
simplify surge-absorption circuit; no VDSS derating is
required).
Overcurrent protection (OCP), overvoltage protection
(OVP), overload protection (OLP), and maximum ON-time
control circuits are incorporated. OVP and OLP go into
a latched mode.
Able to save SMPS design time with present designs and
evaluation processes.
All performance characteristics given are typical values for
circuit or system baseline design only and, unless otherwise
stated, are at the nominal operating voltage and an ambient
temperature of +25°C, unless otherwise stated.
TERMINAL FUNCTIONS
Start-up circuit
VCC (Pin 4)
The start-up circuit detects the VCC pin voltage (pin 4), and
makes the control IC start and stop operation. The power
supply of the control IC (VCC pin input) employs a circuit as
shown in Figure 1. At start-up, C3 is charged through a start-
up resistor R2. The R2 value needs to be set for more than the
hold current of the latch circuit (140 µA max.) and to operate
at the minimum ac input.
Figure 1 – External start-up circuit
If the value of R2 is too high, the C3 charge current will be
reduced. Consequently, it will take longer to reach the
operation start-up voltage. The VCC pin voltage falls immedi-
ately after the control circuit starts its operation. The voltage
drop can be reduced by increasing C3’s capacitance. There-
fore, to maintain the start-up operation, even if the rise of the
bias winding voltage is slow, the VCC pin voltage would not
fall to the operation-stop voltage. However, too large a C3
capacitance will cause an improperly long time to reach the
operation start after the initial power turn on.
In general, SMPS performs its start-up operation properly with
a value of C3 between 4.7 µF and 47 µF, and R2 between
47 kΩ and 150 kΩ for 120 V narrow or universal ac input, and
82 kΩ to 330 kΩ for 200 V narrow ac input.
Sanken Power Devices
from Allegro MicroSystems
1 page  
SwRitecghuinlagtors
Series STR-W6750
Off-Line Quasi-Resonant
Switching Regulators
The time from OLP activation to a latched mode should be
obtained from the following formula if ISSOLP(OLP) is from a
constant-current circuit:
t = CSS × ∆V/ISSOLP (OLP)
where ∆V is the capacitor charging voltage of approximately
5 volts.
However, the ISSOLP(OLP) is voltage dependent on the SS/OLP
pin voltage, and ISSOLP(OLP) drops as the SS/OLP pin voltage
rises. The actual current value does not match the value
calculated in the equation above. Therefore, actual load
conditions should be carefully considered. Also, make sure
that OCP operation at power supply start-up does NOT place
the IC in a latched mode.
OLP timing (0~4.9 V, charging current: 11 mA)
CSS (µF)
0.47 1.0 2.2 3.3 4.7
Time (ms) 209 445 980 1470 2094
During this period, if VCC goes below the UVLO threshold
voltage, the IC does not go into a latch mode, but goes into
intermittent operation. Where the CSS voltage rises to 4.9 V
and VCC does not go below the UVLO threshold voltage, the IC
goes into a latched mode.
NOTE: A large CSS value also results in a longer soft-start
time.
Operation at power supply turn OFF
At power supply turn OFF, voltage on capacitor CSS, which is
externally connected to the SS/OLP pin, is discharged by way
of an internal RESET circuit as shown in Figure 10. The
RESET circuit does not operate in normal operation while the
internal REG circuit operates.
How to deactivate the OLP circuit
To deactivate the OLP circuit while soft start is active, connect
either a 47 kΩ resistor or a Zener diode to the SS/OLP pin
(Figure 11). By doing this, OLP operation is deactivated at
start-up or during an overload status.
Figure 11 – OLP deactivation circuit
FB (Pin 6)
The FB pin is used in either a normal (constant-voltage-control
circuit operation) or in the standby mode. Refer to Standby
Operation (p8) for controlling in the standby mode.
REG circuit (or constant-voltage-control circuit)
Series STR-W6750 adopts the current-mode control circuit for
a REG circuit, which ensures stability with a heavy load. The
peak value of MOSFET drain current (at ON-time) is changed
by comparing the FB pin voltage with the internal VOCPM.
OFF-time becomes quasi-resonant operation synchronized to
the reset signal from a transformer. Where no reset signal is
input from the transformer, it becomes fixed oscillation
frequency (approximately 22 kHz) set by the internal oscillator
circuit. The timing chart is shown in Figure 12, and the
internal circuit diagram of the REG circuit is shown in Figure
13.
Figure 10 – Reset circuit at power turn OFF
www.allegromicro.com
Figure 12 – Constant-voltage control
(quasi-resonant signal ruled out)
5
5 Page 
SwRitecghuinlagtors
Series STR-W6750
Off-Line Quasi-Resonant
Switching Regulators
TRANSFORMER PARAMETERS
Basically, the same type of transformer as that for a conven-
tional quasi-resonant circuit is recommended. The primary
inductance, Lp, is determined by the following:
(VIN D)2
( )Lp =
√2
PO fosc
η
+
VIN
π
fosc
D
√CR
2
where PO = maximum output power,
fosc = minimum oscillating frequency,
D = ON duty cycle at minimum VIN(ac),
η = transformer conversion efficiency (0.9 in the case
of CTV, 0.75 to 0.85 in the case of low output voltage), and
VIN = rectified and smoothed dc input voltage at
minimum VIN(ac).
Turn-ON delay results in duty change in a quasi-resonant
operation, therefore, duty correction is necessary. From the
following, the number of turns, peak switching current (Idp),
corrected duty cycle (D´), delay time (td), and others can be
obtained:
td = π √Lp CR
D´ = D (1 – [fosc td])
Iin = PO/(η2 VIN)
Np = √Lp/AL
Ns = Np (VO + VF)/(D V)
where Iin = average dc input current,
Idp = peak switching current, and
CR = voltage resonance capacitance.
In addition, in the design of the transformer, using 130% of the
estimated peak switching current is recommended to estimate
if the transformer saturates based on the curve of
N × I-limit(AT) vs AL-value (nH/N2).
Instead of performing the calculations above, software that
provides a complete Flyback Transformer Design Tool is
available.
TV application concerns:
Rather than winding with a single thick wire, a thin and
bifilar or trifilar winding across the entire width of bobbin is
recommended.
For windings where Np and +B are a large number of turns,
divisional sandwich winding is recommended.
For an output where a tight regulation is required, winding
with good coupling with S1 (+B) is recommended.
For the +B winding, better coupling by use of litz wire is
required. In case the litz wire does not fit into a bobbin’s
winding width, reduce the wire size, and use several of them in
strands.
For improved thermal design:
Leakage flux of wires close to the core center becomes large.
Eddy current can be reduced by the use of litz wire.
In case the entire winding does not fit into available
winding thickness, reduce the size of wires from outer side.
Wire diameter is determined by actual current and should be
less than 4 A/square mm.
Figure 21 – Example of TV transformer
www.allegromicro.com
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet STR-W6750.PDF ] | |
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