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PDF L5996 Data sheet ( Hoja de datos )

Número de pieza L5996
Descripción 5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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® L5996
5 BIT DYNAMIC DAC CONTROLLER FOR MOBILE CPU
PRELIMINARY DATA
DYNAMIC DAC DETECTION ON CHIP
PROGRAMMABLE OUTPUT FROM 0.925V
TO 2.0V WITH 0.05V AND 0.025V BINARY
STEPS
ULTRA HIGH EFFICIENCY
SEPARATE 5V BIAS SUPPLY AVAILABLE
FOR HIGH EFFICIENCY PERFORMANCE
EXCELLENT OUTPUT ACCURACY ±1%
OVER LINE, LOAD AND TEMPERATURE
VARIATIONS
HIGH PRECISION INTERNAL REFERENCE
DIGITALLY TRIMMED
OPERATING SUPPLY VOLTAGE FROM
4.75V TO 25V
VERY FAST LOAD TRANSIENT
REMOTE SENSING INPUTS
INTERNAL LINEAR REGULATOR 2.5V
/150mA, ±2% PRECISION
POWER MANAGEMENT
- PROGRAMMABLE POWER-UP TIME
- POWER GOOD OUTPUT, SKIP MODE
- OUTPUT OVERVOLTAGE PROTECTION
- OUTPUT UNDERVOLTAGE LOCKOUT
OPERATING FREQUENCY UP TO 1MHz
MEETS INTEL MOBILE PENTIU® III
TQFP32
(7mm x 7mm)
Application
ADVANCED MICROPROCESSOR SUPPLIES
POWERSUPPLYFOR PENTIUM® III INTEL MO-
BILE
DESCRIPTION
The L5996 is a power supply controller that offers
a complete power management for notebook
CPUs of the next generation especially for mobile
Pentium III. A high precise 5 bit digital to analog
converter (DAC) allows to adjust the output volt-
age from 0.925V to 2.0V. Dynamic DAC code
changes are detected on chip in order to switch
the output voltage between 1.3V and 1.45V in
less tahn 100µs.The high precision internal refer-
TYPICAL APPLICATION CIRCUIT
4.75V
to
25V
L5996
PWM SECTIONS
FREQ SETTING
SYNC
DAC
NOSKIP
3.3V
POWER
MANAGEMENT
& SYSTEM
SUPERVISOR
2.5V LIN. REG.
POWER
SECTION
VO
0.925V to 2.0V
D0
D1
D2
D3
D4
POWER GOOD
ENABLE
2.5V
D98IN997A
CPU CORE
Pentium® III
Mobile
CPU CLK
July 1999
1/9
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

1 page




L5996 pdf
L5996
FUNCTIONAL PIN DESCRIPTION
ENABLE(pin1): Enable input. A high level
(>2.4V) enables the device, a low level (<0.8V)
shuts it down. As ENABLE drops below 0.8V, the
drivers are turned off and all internal functions are
disabled except REG5. In this condition the stand
by current is less than 80µA at VIN = 12V.
VIN(pin2): Device supply voltage. Input voltage
range at this pin is 4.75V to 25V and the operat-
ing current requirement at 12V is 650µA.
REG5(pin3): 5V Regulator supply. Used also to
supply the bootstrap capacitor. A minimum 2.2µF
ceramic capacitor connected to PWRGND is re-
quired.
V5SW(pin4): 5V supply line. Connecting to 5V
bus(4.75V to 5.5V) the device is no longer pow-
ered by VIN but by this pin and the internal linear
regulator is disconnected increasing the effi-
ciency.
DISPROT (pin5) Disable Protection Functions. A
high level (3.3V CMOS LOGIC) on this pin dis-
ables the undervoltage and the overvoltage pro-
tection. Tie this pin to VSS for normal operation.
VPROG(pin11): Reference voltage test pin. This
pin provides the DAC output and should be de-
coupled to ground using a 0.22µF ceramic ca-
pacitor. No load has to be connected.
SNSGND(pin12): Remote ground sense. This
pin is internally connected to the low power cir-
cuitry and for a precise output voltage regulation
can be connected to the output capacitor nega-
tive terminal.
VIN2.5(pin13): 2.5V linear supply voltage. Is avail-
able on-chip a linear regulator useful for the 2.5V
bus. A max input voltage of 3.3V is recom-
mended at Iomax (150mA).
VO2.5(pin14): 2.5V linear regulator output. The
linear regulator is realised with an internal NPN
transistor with +/-2% output accuracy. A mini-
mum of 47µF capacitor connected versus
PWRGND is required.
VBG(pin15): Band-gap reference voltage. A min
220nF ceramic capacitor is required to assure the
band gap stability and noise immunity.
VSS(pin16): Signal ground. This pin could be
connected to the PWRGND pin.
SSTART(pin6): Soft Start. The soft-start time is
programmed by an external capacitor connected
between this pin and SGND. The internal current
generator forces 4µA through the capacitor imple-
menting the soft start function.
HRSNS(pin7): Error summing current sense non
inverting input.
LRSNS(pin8): Error summing current sense in-
verting input.
VFB(pin9): Regulator voltage feedback input.
Connect close to the CPU input supply pin realise
an accurate voltage regulation. VFB internally is
connected to the window comparator that is used
to increase the performance during the load tran-
sient.
COMP(pin10): Regulator stability compensation
pin. The compensation is realised internally and
normally it is not necessary to connect any exter-
nal components to this pin.
FREQ(pin17): Connecting an external resistor
versus ground is possible to select the switching
frequency between 100kHz and 1MHz. Using an
Rext=680k the fsw is 100kHz, using an Rext =
40k the fsw is 1MHz. In this condition is recom-
mended to connect the OSC pin to REG5 or to
VSS.
OSC(pin18): Connecting to REG5 is able to set
the switching frequency at 200kHz, connecting to
VSS is able to set the switching frequency at
250kHz. An external pulsed signal, with an ampli-
tude higher than 2.4V, could synchronise the de-
vice. In all these conditions pin FREQ has to be
connected to REG5.
OVP/CURLIM(pin19): Over voltage protection
and reduced current limit window. If the output
voltage reaches the 10% above the programmed
voltage (VPROG) this pin is driven low the high
side driver is turned off and the low, side driver is
turned on. All the internal blocks are active. The
device uses OVP function to discharge the output
during HIGH_TO_LOW core voltage transition.
The pin is driven low also during LOW_TO_HIGH
core voltage transition. The pin will stay low as
5/9

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