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PDF L5993D Data sheet ( Hoja de datos )
| Número de pieza | L5993D | |
| Descripción | CONSTANT POWER CONTROLLER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de L5993D (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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® L5993
CONSTANT POWER CONTROLLER
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
LOW START-UP CURRENT (< 120µA)
CONSTANT OUTPUT POWER VS. SWITCH-
ING FREQUENCY
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100%AND 50% MAXIMUM DUTY CYCLE LIMIT
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE: DIP16 AND SO16N
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
DIP16
SO16N
ORDERING NUMBERS: L5993 (DIP16)
L5993D (SO16)
line or DC-DC power supply applications using a
fixed frequency current mode control.
Based on a standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, over-
current protection with soft start intervention and
”constant power” function for cotrolling throughput
power in multisync monitor SMPS.
RCT
DC
DIS
C-POWER
ISEN
SS
SYNC
1
DC-LIM
15
VCC
8
2
TIMING
+
3
-
25V
+
T 15V/10V -
14 -
+
2.5V
DIS
+
16 -
BLANKING
SQ
R
PWM
OVER CURRENT
13
+
-
1.2V
FAULT
SOFT-START
VREF OK
CLK
DIS
7
2R
1V R
Vref
PWM UVLO
VREF
4
9
13V 10
11
+ 2.5V
E/A
-
5
VC
OUT
PGND
VFB
12
SGND
6
COMP
D97IN765
July 1999
1/22
1 page  
L5993
Figure 3. Quiescent current vs. input voltage.
Iq [m A]
9 .0
8 .5
8 .0
V 14 = 0, V5 = V ref
R t = 4.5Koh m ,Tj = 25 °C
1M hz
500Khz
300Khz
100Khz
7 .5
7 .0
8
10 12 14 16 18 20 22 24
Vc c [V ]
Figure 5. Quiescent current vs. input voltage
and switching frequency.
Iq [mA]
36
Co = 1nF, Tj = 25°C
30
DC = 100%
24 1MHz
18 500KHz
30 0K Hz
12
100KHz
6
0
8 10 12 14 16 18 20 22
Vcc [V]
Figure 7. Vref vs. junction temperature.
Vref [V])
5.1
5.05
5
Vcc = 15V
Iref = 1mA
Figure 4. Quiescent current vs. input voltage
and switching frequency.
Iq [mA]
36
3 0 C o = 1 n F, T j = 2 5 ° C
DC = 0%
24
18
12
6
1M Hz
50 0KHz
30 0KHz
1 00KHz
0
8 10 12 14 16 18 20 22
Vcc [V]
Figure 6. Reference voltage vs. load current.
Vref [V]
5.1
5.05
5
Vcc=15V
Tj = 25°C
4.95
4.9
0
5 10 15 20
Iref [mA]
Figure 8. Vref vs. junction temperature.
Vref [V]
5.1
5.05
Vcc = 15V
Iref= 20mA
25
5
4.95
4.95
4.9
-50 -25 0
25 50 75 100 125 150
Tj (°C)
4.9
-50 -25 0 25 50 75 100 125 150
Tj (°C)
5/22
5 Page 
start capacitor in case of permanent fault, referred
to as ’hiccup” period, is approximately given by:
Thic
≅
4.5
⋅
1
ISSC
+
1
ISSD
⋅
Css
(7)
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
”Hiccup” keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low
(<150µA). This is particularly useful for reducing
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses
when a converter is lightly loaded.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It supplies
the driver of the external switch and therefore ab-
sorbs a pulsed current. Thus it is recommended to
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 25,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is Rg + Rg’, at
turn-off is Rg only.
Pin 10. OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
The driver is made up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
L5993
Figure 25. Turn-on and turn-off speeds adjust-
ment
Rg’
VCC
8
13V
DRIVE &
CONTROL
VC
9
10
OUT
Rg
L5993
D97IN767
PGND
11
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
Figure 26. Pull-Down of the output in UVLO
VREFOK
OUT
10
12
SGND
D97IN538
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltage is 13V, steady state.
Under UVLO conditions an internal circuit (shown
in fig.26) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5993
starts operating, VREFOK is pulled high (refer to fig.
26) and the circuit is disabled.
It is then possible to omit the ”bleeder” resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
11/22
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet L5993D.PDF ] | |
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