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PDF ADM1276 Data sheet ( Hoja de datos )

Número de pieza ADM1276
Descripción Hot Swap Controller and Digital Power and Energy Monitoring
Fabricantes Analog Devices 
Logotipo Analog Devices Logotipo



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Data Sheet
Hot Swap Controller and Digital Power and
Energy Monitoring with PMBus Interface
ADM1276
FEATURES
Controls supply voltages from 2 V to 20 V
370 ns response time to short circuit
Resistor-programmable 5 mV to 25 mV current limit
±1% accurate, 12-bit ADC for current, VIN/VOUT readback
Charge pumped gate drive for multiple external N-channel FETs
High gate drive voltage to ensure lowest RDSON
Foldback for tighter FET SOA protection
Automatic retry or latch-off on current fault
Programmable current-limit timer for SOA
Programmable, multifunction GPO
Power-good status output
Analog UV and OV protection
ENABLE pin
Reports power and energy consumption over time
Peak detect registers for current and voltage
PMBus fast mode compliant interface
20-lead LFCSP
APPLICATIONS
Power monitoring and control/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1276 is a hot swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current and voltage readback via an integrated 12-bit analog-to-
digital converter (ADC), accessed using a PMBus™ interface.
The load current is measured using an internal current sense
amplifier that measures the voltage across a sense resistor in
the power path via the SENSE+ and SENSE− pins. A default
limit of 20 mV is set, but this limit can be adjusted, if required,
using a resistor divider network from the internal reference
voltage to the ISET pin.
The ADM1276 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage—and, therefore,
the load current—is maintained below the preset maximum. The
ADM1276 protects the external FET by limiting the time that the
FET remains on while the current is at its maximum value. This
current-limit time is set by the choice of capacitor connected to
the TIMER pin. In addition, a foldback resistor network can be
used to actively lower the current limit as the voltage across the
FET is increased. This helps to maintain constant power in the
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
FUNCTIONAL BLOCK DIAGRAM
SENSE+
SENSE–
VCC
VCAP
ENABLE
UV
OV
ISET
SS
+×50–
ADM1276-3
LDO
+
1.0V
1.0V +
REF
SELECT
IOUT
+
CHARGE
PUMP
VCP
GATE
DRIVE/
LOGIC
TIMEOUT
CURRENT
LIMIT
1.0V
CURRENT
LIMIT
CONTROL
TIMER ON
GATE
VOUT
FLB
TIMER
TIMER
TIMEOUT
SENSE+
VOUT
IOUT
12-BIT
ADC
LOGIC
AND
PMBus
PWRGD
GPO2/ALERT2
LATCH
SCL
SDA
ADR
GND
Figure 1.
FET and allows the safe operating area (SOA) to be adhered to
in an effective manner.
In case of a short-circuit event, a fast internal overcurrent
detector responds within 370 ns and signals the gate to shut
down. A 1500 mA pull-down device ensures a fast FET response.
The ADM1276 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the
UV and OV pins. A PWRGD signal can be used to detect when
the output supply is valid, using the FLB pin to monitor the output.
A GPO pin can be configured as an output signal that can be
asserted when a programmed current or voltage level is reached.
The 12-bit ADC can measure the current in the sense resistor,
as well as the supply voltage on the SENSE+ pin or the output
voltage. A PMBus interface allows a controller to read current
and voltage data from the ADC. Measurements can be initiated
by a PMBus command. Alternatively, the ADC can run conti-
nuously, and the user can read the latest conversion data whenever
required. As many as four unique PMBus addresses can be selected,
depending on the way that the ADR pin is connected.
The ADM1276 is available in a 20-lead LFCSP with a LATCH pin
that can be configured for automatic retry or latch-off when an
overcurrent fault occurs.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 page




ADM1276 pdf
ADM1276
Data Sheet
SPECIFICATIONS
VCC = 2.95 V to 20 V, VCC ≥ VSENSE+, VSENSE+ = 2 V to 20 V, VSENSE = (VSENSE+ − VSENSE−) = 0 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Operating Voltage Range
Undervoltage Lockout
Undervoltage Hysteresis
Quiescent Current
UV PIN
Input Current
UV Threshold
UV Threshold Hysteresis
UV Glitch Filter
UV Propagation Delay
OV PIN
Input Current
OV Threshold
OV Threshold Hysteresis
OV Glitch Filter
OV Propagation Delay
SENSE+ AND SENSE− PINS
VCC
ICC
IUV
UVTH
UVHYST
UVGF
UVPD
IOV
OVTH
OVHYST
OVGF
OVPD
2.95
2.4
90
0.97 1.0
40 50
2
5
0.97 1.0
50 60
0.5
1.0
20 V
2.7 V
VCC rising
120 mV
5 mA GATE on and power monitor running
100 nA UV ≤ 3.6 V
1.03 V
UV falling
60 mV
7 μs 50 mV overdrive
8 μs UV low to GATE pull-down active
100 nA OV ≤ 3.6 V
1.03 V
OV rising
70 mV
1.5 μs 50 mV overdrive
2 μs OV high to GATE pull-down active
Input Current
Input Imbalance
VCAP PIN
Internally Regulated
Voltage
ISENSEx
IΔSENSE
VVCAP
2.66 2.7
150 μA Per individual pin; SENSE+, SENSE− = 20 V
5 μA IΔSENSE = (ISENSE+) − (ISENSE−)
2.74 V
0 µA ≤ IVCAP ≤ 100 µA; CVCAP = 1 μF
ISET PIN
Reference Select Threshold VISETRSTH
1.35 1.5 1.65 V
If VISET > VISETRSTH, an internal 1 V reference (VCLREF) is used
Internal Reference
VCLREF
1
V Accuracies included in total sense voltage accuracies
Gain of Current Sense
Amplifier
AVCSAMP
50
V/V Accuracies included in total sense voltage accuracies
Input Current
IISET
100 nA VISET ≤ VVCAP
GATE PIN
Maximum voltage on the gate is always clamped to ≤31 V
Gate Drive Voltage
ΔVGATE
ΔVGATE = VGATE − VSENSE+
10 12 14 V 15 V ≥ VCC ≥ 8 V; IGATE ≤ 5 μA
4.5 13 V 20 V ≥ VCC ≥ 15 V; IGATE ≤ 5 μA
8 10 V VSENSE+ = VCC = 5 V; IGATE ≤ 5 μA
4.5 6 V VSENSE+ = VCC = 2.95 V; IGATE ≤ 1 μA
Gate Pull-Up Current
IGATEUP
−20
−30 μA VGATE = 0 V
Gate Pull-Down Current
IGATEDN
Regulation
IGATEDN_REG
45
60
75
μA VGATE ≥ 2 V; VISET = 1.0 V; (SENSE+) − (SENSE−) = 30 mV
Slow
IGATEDN_SLOW 5 10 15 mA VGATE ≥ 2 V
Fast IGATEDN_FAST 750 1500 2000 mA VGATE ≥ 12 V; VCC ≥ 12 V
Gate Holdoff Resistance
20 Ω VCC = 0 V
HOT SWAP SENSE VOLTAGE
Hot Swap Sense Voltage
Current Limit
VSENSECL
19.6 20
20.4 mV VISET > 1.65 V; VFLB > 1.12 V; VGATE = (SENSE+) + 3 V; IGATE = 0 μA;
VSS ≥ 2 V
Foldback Inactive
VGATE = (SENSE+) + 3 V; IGATE = 0 μA; VSS ≥ 2 V
24.6 25
25.4 mV VISET = 1.25 V; VFLB > 1.395 V
19.6 20
20.4 mV VISET = 1.0 V; VFLB > 1.12 V
9.6 10
10.4 mV VISET = 0.5 V; VFLB > 0.57 V
4.6 5
5.4 mV VISET = 0.25 V; VFLB > 0.295 V
Rev. C | Page 4 of 48

5 Page





ADM1276 arduino
ADM1276
Data Sheet
Pin No. Mnemonic
14 VOUT
15 GND
16 GATE
17 SENSE−
18 SENSE+
N/A1
EP
1 N/A means not applicable.
Description
Output Voltage. This pin is used to read back the output voltage using the internal ADC. A 1 kΩ resistor should
be inserted in series between the source of a FET and the VOUT pin.
Ground Pin.
Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET
drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive
controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is
below UVLO.
Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog
current limit. The hot swap operation of the ADM1276 controls the external FET gate to maintain the sense
voltage (VSENSE+ − VSENSE−). This pin also connects to the FET drain pin.
Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the
SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1276 controls
the external FET gate to maintain the sense voltage (VSENSE+ − VSENSE−). This pin is also used to measure the supply
input voltage using the ADC.
Exposed Pad. The exposed pad is located on the underside of the LFCSP package. Solder the exposed pad to the
printed circuit board (PCB) to improve thermal dissipation. The exposed pad can be connected to ground.
Rev. C | Page 10 of 48

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