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PDF 24C03 Data sheet ( Hoja de datos )
| Número de pieza | 24C03 | |
| Descripción | NM24C03 | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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www.DataSheet4U.net
February 1999
NM24C02/03 – 2048-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The NM24C02/03 devices are 2048 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the I2C™ 2-wire protocol and are designed to minimize
device pin count, and simplify PC board layout requirements.
The upper half of the memory of the 24C03 can be disabled (Write
Protected) by connecting the WP pin to VCC. This section of
memory then becomes unalterable unless WP is switched to VSS.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
In addition, this bus structure allows for a maximum of 16K of
EEPROM memory. This is supported by the Fairchild family in 2K,
4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs (not to exceed 16K). For devices with densities greater
than 16K, a different protocol is used. Refer to 32K or higher
densities for additional details.
Fairchild EEPROMs are designed and tested for applications
requiring high endurance, high reliability and low power consump-
tion.
Block Diagram
VCC
VSS
WP
SDA
SCL
START
STOP
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
CONTROL
LOGIC
Features
s Extended operating voltage 2.7V – 5.5V
s 400 kHz clock frequency (F) at 2.7V - 5.5V
s 500µA active current typical
10µA standby current typical
1µA standby typical (L)
0.1µA standby typical (LZ)
s I2C compatible interface
– Provides bidirectional data transfer protocol
s Sixteen byte page write mode
– Minimizes total write time per byte
s Self timed write cycle
Typical write cycle time of 6ms
s Hardware write protect for upper block (NM24C03 only)
s Endurance: 1,000,000 data changes
s Data retention greater than 40 years
s Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
s Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
H.V. GENERATION
TIMING &CONTROL
XDEC
E2PROM
ARRAY
A2 WORD
A1 ADDRESS
A0 COUNTER
R/W YDEC
DIN
DOUT
ACK
CK
DATA REGISTER
DOUT
DS500069-1
© 1998 Fairchild Semiconductor Corporation
NM24C02/03 Rev.C
1
www.fairchildsemi.com
1 page  
Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)
Symbol
Parameter
100 kHz
Min Max
400 kHz
Min Max
fSCL SCL Clock Frequency
TI Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum VIN
Pulse width)
100
100
400
50
tAA SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9
tBUF Time the Bus Must Be Free before
a New Transmission Can Start
4.7
1.5
tHD:STA
tLOW
tHIGH
tSU:STA
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
4.7
4.0
4.7
0.6
1.5
0.6
0.6
tHD:DAT
Data in Hold Time
0
0
tSU:DAT
Data in Setup Time
250
100
tR SDA and SCL Rise Time
1 0.3
tF SDA and SCL Fall Time
300 300
tSU:STO
Stop Condition Setup Time
4.7
0.6
tDH Data Out Hold Time
300
50
tWR
(Note 2)
Write Cycle Time - NM24C02/03
- NM24C02/03L, NM24C02/03LZ
10
15
10
15
Units
kHz
ns
µs
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
ms
Note 2: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
NM24C02/03 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
NM24C02/03 Rev.C
5 www.fairchildsemi.com
5 Page 
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read operations:
current address read, random read, and sequential read.
Current Address Read
Internally the NM24C02/03 contains an address counter that
maintains the address of the last byte accessed, incremented by
one. Therefore, if the last access (either a read or write) was to
address n, the next read operation would access data from
address n + 1. Upon receipt of the slave address with R/W set to
one, the NM24C02/03 issues an acknowledge and transmits the
eight bit byte. The master will not acknowledge the transfer but
does generate a stop condition, and therefore the NM24C02/03
discontinues transmission. Refer to Figure 8 for the sequence of
address, acknowledge and data transfer.
Random Read
Random read operations allow the master to access any memory
location in a random manner. Prior to issuing the slave address
with the R/W bit set to one, the master must first perform a
“dummy” write operation. The master issues the start condition,
slave address and then the byte address it is to read. After the
byte address acknowledge, the master immediately reissues the
start condition and the slave address with the R/W bit set to one.
This will be followed by an acknowledge from the NM24C02/03
and then by the eight bit byte. The master will not acknowledge the
transfer but does generate the stop condition, and therefore the
NM24C02/03 discontinues transmission. Refer to Figure 9 for the
address, acknowledge and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current address read
or random access read. The first word is transmitted in the same
manner as the other read modes; however, the master now
responds with an acknowledge, indicating it requires additional
data. The NM24C02/03 continues to output data for each ac-
knowledge received. The read operation is terminated by the
master not responding with an acknowledge or by generating a
stop condition.
The data output is sequential, with the data from address n
followed by the data from n + 1. The address counter for read
operations increments all word address bits, allowing the entire
memory contents to be serially read during one operation. After
the entire memory has been read, the counter "rolls over" and the
NM24C02/03 continues to output data for each acknowledge
received. Refer to Figure 10 for the address, acknowledge, and
data transfer sequence.
Current Address Read (Figure 8)
Bus Activity:
Master
S
T
A
R
T
SDA Line
S
Bus Activity:
NM24C02/03
Random Read (Figure 9)
Bus Activity:
Master
S
T
A
R
T
SLAVE
ADDRESS
SDA Line
S
Bus Activity:
NM24C02/03
SLAVE
ADDRESS
A
C
K
DATA
S
T
O
P
P
NO
A
C
K
DS500069-17
WORD
ADDRESS
S
T
A SLAVE
R ADDRESS
T
S
AA
CC
KK
A
C
K
DATA n
S
T
O
P
P
NO
A
C
K
DS500069-18
Sequential Read (Figure 10)
Bus Activity:
Master
Slave
Address
SDA Line
Bus Activity:
NM24C02/03
A
C
K
Data n +1
A AA
C CC
K KK
Data n +1
Data n + 2
Data n + x
S
T
O
P
P
NO
A
C
K
DS500069-19
NM24C02/03 Rev.C
11 www.fairchildsemi.com
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 24C03.PDF ] | |
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