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PDF L4990 Data sheet ( Hoja de datos )

Número de pieza L4990
Descripción PRIMARY CONTROLLER
Fabricantes STMicroelectronics 
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L4990
® L4990A
PRIMARY CONTROLLER
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
LOW START-UP CURRENT < 0.45mA
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100% AND 50% MAXIMUM DUTY CYCLE
LIMIT
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
DISABLE LATCHED
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE: DIP16 AND SO16W
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
BLOCK DIAGRAM
MULTIPOWER BCD TECHNOLOGY
DIP16
SO16W
ORDERING NUMBERS: L4990/L4990A(DIP16)
L4990D/L4990AD (SO16W)
line or DC-DC power supply applications using a
fixed frequency current mode control.
Based on a standard current mode PWM control-
ler this device includes some features as pro-
grammable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection
and for power management), precise maximum
Duty Cycle Control, 100ns (typ) leading edge
blanking on current sense, pulse by pulse current
limit and overcurrent protection with soft start in-
tervention.
2
RCT
3
DC
+
-
14
DIS
-
+
2.5V
DIS
ISEN
SS
OVER CURRENT
13
+
-
1.2V
7
1V
SYNC
1
TIMING
T
DC-LIM
15
VCC
8
25V
16V/10V
+
-
Vref
PWM UVLO
VREF
4
9
VC
BLANKING
PWM
FAULT
SOFT-START
2R
R
12
SGND
SQ
R
VREF OK
CLK
DIS
6
COMP
13V 10
OUT
2.5V
+
E/A
-
11
PGND
5
VFB
D98IN1002
July 1999
1/24

1 page




L4990 pdf
referenced to 1.2V detects primary over-current
conditions. On detection of an overcurrent fault
the output is immediately shutdown and the fault
is also latched. A Fault Reset Delay is imple-
mented by discharging the external Soft Start
(SS) timing capacitor before resetting the fault
latch and initiating a softstart cycle.
In case of a continuous fault condition the SS ca-
pacitor is charged to 5V before being discharged
again, to ensure that the fault frequency does not
exceed the programmed soft start frequency.
Duty Cycle Limit
A simple connection between the DC-LIM and the
available Vref activates an internal T- FlipFlop lim-
iting the DC to about 50%. If this pin is not con-
nected or grounded, the limit of the duty cycle is
extended to about 100%
Duty Cycle Control
Duty Cycle DC is externally programmed by set-
ting a voltage between 1V (0% DC) and 3V
(100% DC) at the DC pin. The programmed volt-
age is compared with the oscillator CT capacitor
charging waveform to determine the maximum
ON-time in each period. This function gives a fine
control of DC.
If this pin is floating the maximum duty cycle de-
pends on DC-LIM status.
Synchronization
A SYNC pin eases Synchronization of the IC to
the external world ( e.g. another IC working in
L4990 - L4990A
parallel or to TV/monitor sync signal).
In TV/monitor applications the timing components
RT, CT are set for a frequency lower than the
minimum TV sync frequency. When the TV circuit
has powered-up it takes over and the system fre-
quency is that of the SYNC. Duty Cycle is control-
lable using the DC function.
In parallel operation of several IC’s no Mas-
ter/Slave designation is required as the higher fre-
quency IC is automatically the master. Controllers
to be synchronized have their SYNC pins tied to-
gether and each SYNC pin operates as a bidirec-
tional circuit. The first IC to drive its SYNC pin is
the master and it initiates a discharge of the CT
timing capacitor of every controller. The Sync in-
put signal is edge-triggered and sets an internal
”sync latch” which ensures full discharge of CT.
Disable Function
The DIS pin performs a logic level latched-shut-
down function. When pulled above 2.5V it shuts
down the complete IC with a standby current of
<270µA (typ).
To reset the IC the VCC pin must be pulled-down
below the lower UVLO threshold (10V).
Leading Edge Blanking (LEB)
An LEB interval of 100ns has been incorporated
into the IC to blank out the current sense signal
during the first 100ns from switch turn-on.
This provides noise immunity to turn-on spikes
and reduces external RC filtering requirements on
the current-sense signal.
Figure 1. Quiescent current vs. input voltage.
(X = 7.6V and Y = 8.4V for L4990A)
Iq [m A ]
30
V1 4 = 0 , O SC= d isa bled
20 T j = 25°C
8
6
1
0 .8
0 .6
0 .4
0 .2
0
0
XY
4 8 12 16 20 24
Vcc [V]
Figure 2. Quiescent current vs. input voltage
(after disable).
Iq [uA]
300
270
240
V14 = Vref
Tj = 25°C
210
8 10 12 14 16 18 20 22 24
Vcc [V ]
5/24

5 Page





L4990 arduino
L4990 - L4990A
Tss
3
Rsense
ISSC
IQpk
Css
(6)
where Rsense is the current sense resistor (see pin
13) and IQpk is the switch peak current (flowing
through Rsense), which depends on the output
load. Usually, CSS is selected for a TSS in the or-
der of milliseconds.
Figure 23. Regulation characteristic and re-
lated quantities
VOUT
D.C.M.
A
C.C.M.
TON
D97IN495
B
D
ISHORT IOUT(max)
IQpk
1-2 ·IQpk
IQpk(max)
C
TON(min)
IOUT
Figure 24. Hiccup mode operation.
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 23, pulse-by-pulse
current limitation is somehow effective as long as
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 24 illustrates the
operation.
The oscillation frequency appearing on the soft-
start capacitor in case of permanent fault, referred
to as ’hiccup” period, is approximately given by:
Thic
4.5
1
ISSC
+
1
ISSD
Css
(7)
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
IOUT
ISEN
FAULT
SS
5V
0.5V
SHORT
7V
time
Thic D97IN496
11/24

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