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PDF IDT72V3682 Data sheet ( Hoja de datos )

Número de pieza IDT72V3682
Descripción 3.3 VOLT CMOS SyncBiFIFO
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT72V3682 Hoja de datos, Descripción, Manual

3.3 VOLT CMOS SyncBiFIFOTM
16,384 x 36 x 2
32,768 x 36 x 2
65,536 x 36 x 2
IDT72V3682
IDT72V3692
IDT72V36102
FEATURES
Memory storage capacity:
IDT72V3682 – 16,384 x 36 x 2
IDT72V3692 – 32,768 x 36 x 2
IDT72V36102 – 65,536 x 36 x 2
Supports clock frequencies up to 100MHz
Fast access times of 6.5ns
Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
Two independent clocked FIFOs buffering data in opposite direc-
tions
Mailbox bypass register for each FIFO
Programmable Almost-Full and Almost-Empty flags
Microprocessor Interface Control Logic
FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
Pin compatible to the lower density parts, IDT72V3622/72V3632/
72V3642/72V3652/72V3662/72V3672
Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
FFA/IRA
AFA
Mail 1
Register
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Write
Pointer
Read
Pointer
FIFO 1
Status Flag
Logic
MBF1
36
EFB/ORB
AEB
FS0
FS1
A0 - A35
EFA/ORA
AEA
MBF2
Programmable Flag Timing
Offset Registers
Mode
16
FIFO 2
Status Flag
Logic
Read
Write
36
Pointer
Pointer
RAM
ARRAY
16,384 x 36
32,768 x 36
65,536 x 36
Mail 2
Register
FWFT
B0 - B35
FFB/IRB
AFB
36
FIFO2,
Mail2
Reset
Logic
RST2
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
4679 drw 01
www.DataSheet4U.netIDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-4679/3

1 page




IDT72V3682 pdf
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
PIN DESCRIPTIONS (CONTINUED)
COMMERCIALTEMPERATURERANGE
Symbol
Name
I/O
Description
MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
Select
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a
LOW level selects FIFO2 output register data for output.
MBB
MBF1
Port B Mailbox
Select
Mail1 Register
Flag
MBF2
Mail2 Register
Flag
RST1
FIFO1 Reset
RST2
FIFO2 Reset
W/RA
W/RB
Port A Write/
Read Select
Port B Write/
Read Select
I A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a
LOW level selects FIFO1 output register data for output.
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1
is reset.
O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when
FIFO2 is reset.
I ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA
and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
I ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmustoccur
while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB
and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
5

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IDT72V3682 arduino
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFOTM
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
highest numbered input is used as the most significant bit of the binary number
ineachcase. Validprogrammingvaluesfortheregistersrangesfrom1to16,380
for the IDT72V3682; 1 to 32,764 for the IDT72V3692; and 1 to 65,532 for the
IDT72V36102. AfteralltheoffsetregistersareprogrammedfromportA,theport
B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal
operation. See Figure 3 for relevant offset register parallel programming timing
diagram.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by port A Chip Select
(CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are in the high-
impedance state when either CSAor W/RA is HIGH. The A0-A35 outputs are
active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
byaLOW-to-HIGHtransitionofCLKAwhen CSAis LOW, W/RAisLOW,ENA
is HIGH, MBA is LOW, and EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on port A are independent of any concurrent port B operation. Write and
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
The port B control signals are identical to those of port A with the exception
that the port B Write/Read select (W/RB) is the inverse of the port A Write/Read
select (W/RA). The state of the port B data (B0-B35) outputs is controlled by the
port B Chip Select (CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either CSB is HIGH or W/RB is
COMMERCIALTEMPERATURERANGE
LOW. The B0-B35 outputs are active when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhenCSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,
and FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-
to-HIGH transition of CLKB whenCSB is LOW, W/RB is HIGH, ENB is HIGH,
MBB is LOW, and EFB/ORB is HIGH (see Table 3) . FIFO reads and writes
on port B are independent of any concurrent port A operation. Write and Read
cycle timing diagrams for Port B can be found in Figure 5 and 6.
The setup and hold time constraints to the port Clocks for the port Chip Selects
and Write/Read selects are only for enabling write and read operations and are
not related to high-impedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port’s Chip Select and Write/Read select may change
states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
the next word written is automatically sent to the FIFO’s output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of the
ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port’s Chip Select, Write/Read
select, Enable, and Mailbox select.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA W/RA ENA
MBA CLKA
Data A (A0-A35) I/O
HXX X X
High-Impedance
LHL X X
Input
LHH L
Input
LHH H
Input
LLL L X
Output
LLH L
Output
LLL H X
Output
LLH H
Output
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB W/RB
ENB
MBB CLKB
Data B (B0-B35) I/O
HXX X X
High-Impedance
LLL X X
Input
LLH L
Input
LLH H
Input
LHL L X
Output
LHH L
Output
LHL H X
Output
LHH H
Output
11
Port Function
None
None
FIFO1 write
Mail1 write
None
FIFO2 read
None
Mail2 read (set MBF2 HIGH)
Port Function
None
None
FIFO2 write
Mail2 write
None
FIFO1 read
None
Mail1 read (set MBF1 HIGH)

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