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PDF YSS944 Data sheet ( Hoja de datos )

Número de pieza YSS944
Descripción (YSS940 - YSS944) ADAMB Advanced Digital Audio Multi channel decode processor
Fabricantes YAMAHA 
Logotipo YAMAHA Logotipo



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YSS944/943/940
ADAMB
Advanced Digital Audio Multi channel decode processor
„ Outline
The YSS944 (ADAMB-f)/YSS943 (ADAMB-b)/YSS940 (ADAMB-nd) is an audio decoding digital signal
processor that integrates onto a single chip the various digital signal processing functions required for AV
amplifiers, etc. It includes an advanced 32-bit floating-point DSP and is able to decode a variety of audio
formats.
[Note]
The contents described in this manual are implemented by downloading boot firmware.
For detailed information about the boot firmware, please contact YAMAHA.
The YSS943 cannot execute DTS-ES and DTS Neo:6 decoding.
The YSS940 cannot execute any decoding related to DTS (DTS, DTS-ES, DTS 96/24, and DTS Neo:6).
„ Features
Supports various types of decoding up to 7.1 channels (5.1/6.1/7.1 channels selectable).
5.1-channel decoding of Dolby Digital (AC-3), DTS, AAC.
6.1-channel decoding of Dolby Digital EX, DTS-ES.
DTS 96/24 decoding and audio interface clock division/switching functions.
Dolby Pro Logic IIx and DTS Neo:6 decoding
Tone control and bass management functions
Function modification/expansion by downloading firmware to on-chip memory
Lip-sync function that enables synchronization of voice and video with variable voice delay
Supports sampling frequencies up to 192 kHz during PCM playback.
1/2 down sampling function when two PCM channels are played back
Dolby Digital/DTS/AAC decode information output function (can be read by microprocessor)
High-speed/high-accuracy operation by 32-bit floating-point DSP
Operating frequency: 180 MHz (178.176 MHz)
Data bus width: 32 bits (24-bit mantissa and 8-bit exponent)
Multiplier/adder: 32 bits × 32 bits + 55 bits 55 bits (47-bit mantissa and 8-bit exponent)
No external memory needed (external memory is used when delay is increased.)
Eight general I/O ports
On-chip PLL for generation of high-speed internal operating clock
Supply voltage: 1.2 V (core block) and 3.3 V (pin block)
Low power consumption: about 210 mW (standard value during Dolby Digital decoding)
Si-gate CMOS process
Lead-free plating LQFP144 package (YSS944-VZ, YSS943-VZ, and YSS940-VZ)
[Note]
“Dolby,” ”Dolby Pro Logic IIx,” and “AC-3” are trademarks of Dolby Laboratories.
“DTS,” “DTS-ES,” “DTS 96/24,” and “DTS Neo:6” are trademarks of Digital Theater Systems, Inc.
„ Applications
AV amplifiers for home theaters
Car audio systems
www.DataSheet4U.com
YSS944/943/940 CATALOG
CATALOG No.: LSI-4SS944A31
2005.6

1 page




YSS944 pdf
YSS944/943/940
„ Pin Functions
Type
Pin
No.
Power supply
9
33
45
60
85
100
121
136
5
6
15
22
23
36
50
51
63
64
70
71
79
80
88
89
95
107
108
119
120
127
128
137
138
142
143
144
4
7
8
14
20
21
35
41
42
48
49
Pin Name
VDD1
I/O Function
Note 1)
- Power supply pins for pin block (Typ. 3.3 V).
VDD2
- Power supply pins for core block (Typ. 1.2 V).
AVDDR
- Power supply pin 1 for PLL analog block (Typ. 3.3 V).
Be sure to insert a 0.1 µF capacitor between the AVDDR and AVSSR
pins.
AHVDD
- Power supply pin 2 for PLL analog block (Typ. 3.3 V).
Be sure to insert a 0.1 µF capacitor between the AHVDD and AHVSS
pins.
AHVDDG - Power supply pin 3 for PLL analog block (Typ. 3.3 V).
Be sure to insert a 0.1 µF capacitor between the AHVDDG and
AHVSSG pins.
DVDD
- Power supply pin for PLL digital block (Typ. 1.2 V).
Be sure to insert a 0.1 µF capacitor between the DVDD and DVSS
pins.
VSS - Ground pins
5

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YSS944 arduino
YSS944/943/940
Audio interface
- Master clock, bit clock, word clock, and four serial data (8ch) for input and output are provided
respectively.
- Various audio interface formats are supported.
- The bit clock rate is fixed to 64 fs.
- Supported sampling frequencies are 32 kHz, 44.1 kHz, 48 kHz, 64 kHz, 88.2 kHz, 96 kHz, 128 kHz,
176.4 kHz, and 192 kHz.
- The bit clock and word clock on the output side have switchable input/output, and can therefore be
used as either master or slave.
- A clock divider/switching function is included to enable adjustment of the input/output sampling
frequency for DTS 96/24, etc.
Audio data output channel control
- Audio output data can be output to any of the channels for the SDO3 to SDO0 pins.
Bypass
- Output of SDI data to SDO can bypass the internal core logic.
User mute
- Output channels can be muted via the microprocessor interface.
External memory interface
- Up to 4 Mb of SRAM can be connected for input delay and/or output delay.
- Access time can be adjusted via register settings.
Input delay (lip sync)
- Input delay for adjusting synchronization between video and audio can be implemented when using
external memory.
Output delay
- 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 192 kHz can be
implemented without using external memory (some exceptions).
- 3-/4-/5-/6-/7-/8-channel output delay with an output sampling frequency of up to 96 kHz can be
implemented using external memory.
Stream detection
- Encoding format detection
- Zero detection
- Input sampling frequency detection
Auto mute
- All channels are muted automatically by detection of noise generation factor.
Status ports
- Consecutive-zero data input detection:
- Auto mute period output:
- Interrupt request output:
1 pin.
1 pin.
1 pin.
General purpose I/O port
- 8 general purpose I/O ports are available.
- Input and output mode can be switched by register setting.
Internal operating clock generation
- Generates the high-speed internal operating clock by on-chip PLL.
Power-up/power-down
- Enables power-up/power-down control of the LSI via register settings.
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