PDF DS31406 Data sheet ( Hoja de datos )

Número de pieza	DS31406
Descripción	Single DPLL Timing IC
Fabricantes	Maxim Integrated Products
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No Preview Available ! ABRIDGED DATA SHEET 19-5711; Rev 0; 12/10 DS31406 2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter General Description The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem which has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS. For telecom systems, the DS31406 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31406 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813, and G.8262. Applications Frequency Conversion Applications in a Wide Variety of Equipment Types Telecom Line Cards or Timing Cards with Any Mix of SONET/SDH, Synchronous Ethernet and/or OTN Ports in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Base Stations Ordering Information PART DS31406GN+ TEMP RANGE -40C to +85C PIN-PACKAGE 256 CSBGA +Denotes a lead(Pb)-free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. Features  Two Input Clocks  Differential or CMOS/TTL Format  Any Frequency from 2kHz to 750MHz  Fractional Scaling for 64B/66B and FEC Scaling (e.g., 64/66, 237/255, 238/255) or Any Other Downscaling Requirement  Continuous Input Clock Quality Monitoring  Automatic or Manual Clock Selection  Two 2/4/8kHz Frame Sync Inputs  High-Performance DPLL  Hitless Reference Switching on Loss of Input  Automatic or Manual Phase Build-Out  Holdover on Loss of All Inputs  Programmable Bandwidth, 0.5mHz to 400Hz  Seven Digital Frequency Synthesizers  Produce Any 2kHz Multiple Up to 77.76MHz  Per-DFS Clock Phase Adjust  Three Output APLLs  Output Frequencies to 750MHz  High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement  Less than 1ps RMS Output Jitter  Simultaneously Produce Three Low-Jitter Rates from the Same Reference (e.g., 622.08MHz for SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for 10GE)  14 Output Clocks in Seven Groups  Nearly Any Frequency from <1Hz to 750MHz  Each Group Slaves to a DFS Clock, Any APLL Clock, or Any Input Clock (Divided and Scaled)  Each Has a Differential Output (3 CML, 4 LVDS/ LVPECL) and Separate CMOS/TTL Output  32-Bit Frequency Divider Per Output  Two Sync Pulse Outputs: 8kHz and 2kHz  General Features  Suitable Line Card IC or Timing Card IC for Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU  Accepts and Produces Nearly Any Frequency Up to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1, NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M, 156.25M, and Nx19.44M Up to 622.08M  Internal Compensation for Local Oscillator Frequency Error  SPI™ Processor Interface  1.8V Operation with 3.3V I/O (5V Tolerant) Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. www.DataSheet4U.net 1 page ABRIDGED DATA SHEET DS31406 Output Clock Features  14 output clock signals in seven groups  Output clock groups OC1, OC2, OC3 have a very high-speed differential output (current-mode logic, ≤ 750MHz) and a separate CMOS/TTL output (≤ 125MHz)  Output clock groups OC4–OC7 have a high-speed differential output (LVDS/LVPECL, ≤ 312.5MHz) and a separate CMOS/TTL ouptut (≤ 125MHz)  Each output can be any frequency from < 1Hz to max frequency stated above  Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, microprocessor clock frequencies, and much more  Internal clock muxing allows each output group to slave to its associated DFS block, any of the APLLs, or any input clock (after being divided and scaled)  Outputs sourced directly from APLLs have less than 1ps RMS output jitter  Outputs sourced directly from DFS blocks have approximately 40ps RMS output jitter  Optional 32-bit frequency divider per output  8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can be disciplined by a 2kHz or 8kHz frame sync input  Per-output delay adjustment  Per-output enable/disable  All outputs disabled during reset General Features  SPI serial microprocessor interface  Four general-purpose I/O pins  Register set can be write protected  Operates from a 12.8MHz, 25.6MHz, 10.24MHz, 20.48MHz, 10MHz, 20MHz, 19.44MHz, or 38.88MHz local oscillator  On-chip watchdog circuit for the local oscillator  Internal compensation for local oscillator frequency error Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to www.maxim-ic.com/DS31406 and click on Request Full Data Sheet. 5 5 Page

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