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PDF TDA8035HN Data sheet ( Hoja de datos )
| Número de pieza | TDA8035HN | |
| Descripción | Smart card interface | |
| Fabricantes | NXP Semiconductors | |
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TDA8035HN
Smart card interface
Rev. 1.0 — 19 April 2011
Product data sheet
1. General description
The TDA8035 is the cost efficient successor of the well established integrated contact
smart card reader IC TDA8024. It offers a high level of security for the card performing
current limitation, short circuit detection, ESD protection as well as supply supervision.
Operating in 3 V supply domain, the current consumption during the standby mode of the
contact reader is very low and is therefore the ideal component for a power efficient
contact reader.
2. Features and benefits
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2.1 Protection of the contact smart card
Thermal and short-circuit protections on all card contacts
Vcc regulation:
5 V, 3 V, 1.8 V ± 5 % on 2 × 220 nF multilayer ceramic capacitors with low ESR
current spikes of 40 nA/s (Vcc = 5 V and 3 V) or 15 nA/s (Vcc = 1.8 V) up to
20 MHz, with controlled rise and fall times, filtered overload detection
approximately 120 mA
Automatic activation and deactivation sequences initiated by software or by hardware
in the event of a short-circuit, card take-off, overheating, falling VREG VDD(INTF),VDDP
Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV)
Supply supervisor for killing spikes during power on and off:
threshold internally fixed
externally by a resistor bridge
2.2 Easy integration into your contact reader
SW compatible to TDA8024 and TDA8034
5 V, 3 V, 1.8 V smart card supply
DC/DC converter for Vcc generation separately powered from 2.7 V to 5.5 V supply
(VDDP and GNDP)
Very low power consumption in Deep Shutdown mode
Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8 )
External clock input up to 26 MHz
Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with
synchronous frequency changes of fXTAL, fXTAL/2, fXTAL/4 or fXTAL/8
Non-inverted control of pin RST using pin RSTIN
Built-in debouncing on card presence contact
Multiplexed status signal using pin OFFN
1 page  
NXP Semiconductors
7. Pinning information
7.1 Pinning
TDA8035HN
Smart card interface
terminal 1
index area
I/OUC 1
PORADJ 2
CMDVCCN 3
VDD(INTF) 4
CLKDIV1 5
CLKDIV2 6
EN_5V/3VN 7
EN_1.8VN 8
TDA8035
24 CLK
23 RST
22 VCC
21 VUP
20 SAP
19 SBP
18 VDDP
17 SBM
Transparent top view
Fig 2. Pin configuration HVQFN32
001aan746
7.2 Pin description
Table 3. Pin description
Symbol
Pin
Supply
I/OUC
1
VDD(INTF)
PORADJ
2
VDD(INTF)
Type
I/O
I
CMDVCCN
VDD(INTF)
CLKDIV1www.DataSheet4U.net
CLKDIV2
EN_5V/3VN
3
4
5
6
7
VDD(INTF)
VDD(INTF)
VDD(INTF)
VDD(INTF)
VDD(INTF)
I
supply
I
I
I
EN_1.8 VN
RSTIN
OFFN
8
9
10
VDD(INTF)
VDD(INTF)
VDD(INTF)
I
I
O
GND
XTAL1
XTAL2
VREG
SAM
11
12
13
14
15
-
VDD(INTF)
VDD(INTF)
VDDP
VDDP
supply
I
O
supply
I/O
GNDP
16
-
supply
Description
host data I/O line (internal 10k pullup resistor to VDD(INTF) )
Input for VDD(INTF) supervisor. PORADJ threshold can be changed
with an external R bridge
start activation sequence input from the host (active LOW)
interface supply voltage
control with CLKDIV2 for choosing CLK frequency see Table 4
control with CLKDIV1 for choosing CLK frequency see Table 4
control signal for selecting Vcc = 5 V (HIGH) or Vcc = 3 V (LOW) if
EN_1.8 VN = High
control signal for selecting Vcc = 1.8V (low)
card reset input from the host (active HIGH)
NMOS interrupt to the host (active LOW) with 10k internal pull up
resistor to VDD(INTF) (See fault detection)
ground
crystal connection
crystal connection
Internal supply voltage
DC/DC converter capacitor ; connected between SAM and SAP; C =
330nF with ESR < 100mΩ
DC/DC converter power supply ground
TDA8035HN
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 19 April 2011
© NXP B.V. 2011. All rights reserved.
5 of 32
5 Page 
NXP Semiconductors
TDA8035HN
Smart card interface
8.4 I/O circuitry
The three data lines I/O, AUX1 and AUX2 are identical.
The Idle state is realized by both lines (I/O and I/OUC) being pulled HIGH via a 10 k
resistor (I/O to VCC and I/OUC to VDD(INTF)).
I/O is referenced to VCC, and I/OUC to VDD(INTF), thus allowing operation with
VCC ≠ VDD(INTF).
The first side on which a falling edge occurs becomes the master. An anti-latch circuit
disables the detection of falling edges on the other line, which becomes a slave.
After a time delay td(edge), the logic 0 present on the master side is transmitted to the slave
side.
When the master side returns to logic 1, the slave side transmits the logic 1 during the
time delay tpu, and then both sides return to their Idle states.
This active pull-up feature ensures fast Low to High transitions; it is able to deliver more
than 1 mA up to an output voltage of 0.9 VCC on a 80 pF load. At the end of the active
pull-up pulse, the output voltage only depends on the internal pull-up resistor, and on the
load current.
The current to/from the cards I/O lines is internally limited to 15 mA.
The maximum frequency on these lines is 1.5 MHz.
www.DataSheet4U.net
TDA8035HN
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 19 April 2011
© NXP B.V. 2011. All rights reserved.
11 of 32
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