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PDF FAN6920MR Data sheet ( Hoja de datos )
| Número de pieza | FAN6920MR | |
| Descripción | Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller | |
| Fabricantes | Fairchild Semiconductor | |
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April 2011
FAN6920MR
Integrated Critical-Mode PFC and Quasi-Resonant
Current-Mode PWM Controller
Features
Integrated PFC and Flyback Controller
Critical-Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal Minimum 5µs tOFF for QR PWM Stage
Internal 5ms Soft-Start for PWM
Brownout Protection
High / Low Line Over-Power Compensation
Auto-Recovery Over-Current Protection
Auto-Recovery Open-Loop Protection
Externally Auto-Recovery Triggering (RT Pin)
Adjustable Over-Temperature Protection
VDD Pin and Output Voltage OVP (Auto-Recovery)
Internal Over-Temperature Shutdown (140°C)
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Description
The highly integrated FAN6920MR combines Power
Factor Correction (PFC) controller and quasi-resonant
PWM controller. Integration provides cost-effective
design and reduces external components.
For PFC, FAN6920MR uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power-factor correction. With an
innovative THD optimizer, FAN6920MR can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6920MR provides several functions to
enhance the power system performance: valley
detection, green-mode operation, and high / low line
over-power compensation. Protection functions include
secondary-side open-loop and over-current with auto-
recovery protection; external auto-recovery triggering;
adjustable over-temperature protection by RT pin; and
external NTC resistor, internal over-temperature
shutdown, VDD pin OVP, and DET pin over-voltage for
output OVP, and brown-in / out for AC input voltage
UVP.
The FAN6920MR controller is available in a 16-pin
small-outline package (SOP).
Ordering Information
www.DataSheet4U.com
Part Number OLP Mode
FAN6920MRMY Recovery
Operating
Temperature Range
-40°C to +105°C
Package
16-Pin Small Outline Package (SOP)
Packing
Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
www.fairchildsemi.com
1 page  
Pin Definitions (Continued)
Pin #
6
7
8
9
10
11
12
13
14
15
16
Name
OPFC
VDD
OPWM
GND
DET
FB
RT
VIN
ZCD
NC
HV
Description
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage
is 15.5V.
Power supply. The threshold voltages for startup and turn-off are 12V and 7V, respectively. The
startup current is less than 30µA and the operating current is lower than 10mA.
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5V.
The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
Producing an offset voltage to compensate the threshold voltage of PWM current limit for over-
power compensation. The offset is generated in accordance with the input voltage when the
PWM switch is on.
Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
Providing output over-voltage protection. A voltage comparator is built in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
over voltage and this flat voltage are higher than 2.5V, the controller stops all PFC and PWM
switching operation. The protection mode is auto-recovery.
Feedback voltage pin used to receive the output voltage level signal to determine PWM gate duty
for regulating output voltage. The FB pin voltage can also activate open-loop, overload protection
and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2V
for more than 50ms.The input impedance of this pin is a 5kΩequivalent resistance. A 1/3
attenuator is connected between the FB pin and the input of the CSPWM/FB comparator.
Adjustable over-temperature protection and external protection triggering. A constant current
flows out from the RT pin. When RT pin voltage is lower than 0.8V (typical), protection is
activated and stops PFC and PWM switching operation. This protection is auto-recovery.
Line-voltage detection for brownin / out protections. This pin can receive the AC input voltage
level through a voltage divider. The voltage level of the VIN pin is not only used to control
RANGE pin’s status, but it can also perform brownin / out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching
cycle. When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and
the controller stops PFC switching. This can be realized with an external circuit if disabling the
PFC stage is desired.
No connection
High-voltage startup pin is connected to the AC line voltage through a resistor (100kΩtypical) for
providing a high charging current to VDD capacitor.
www.DataSheet4U.com
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
5
www.fairchildsemi.com
5 Page 
Electrical Characteristics (Continued)
VDD=15V, TA=-40°C~105°C (TA=TJ), unless otherwise specified.
Symbol
Parameter
VCTRL-PFC-BM
Threshold Voltage on FB Pin for
PFC Burst Mode
Conditions
RANGE Pin Internally
Open
RANGE Pin Internally
Ground
VCTRL-PFC-ON
Threshold Voltage on FB Pin for
PFC Normal Operating
tPFC-BM
tPFC-ON
Debounce Time for PFC Burst
Mode
Debounce Time for PFC
Recovery to Normal Operating
tSTARTER-PWM Start Timer (Time-Out Timer)
PWM Output Section
VCLAMP
PWM Gate Output Clamping
Voltage
VOL PWM Gate Output Voltage Low
VOH PWM Gate Output Voltage High
tR PWM Gate Output Rising Time
tF PWM Gate Output Falling Time
Current Sense Section
tPD Delay to Output
VLIMIT
Limit Voltage on CSPWM Pin for
Over-Power Compensation
VSLOPE
Slope Compensation(4)
tON-BNK
VCS-FLOATING
tCS-H
Leading-Edge Blanking Time
CSPWM Pin Floating VCSPWM
Clamped High Voltage
Delay Time, CS Pin Floating
PFC Normal Operating
Burst Mode
PFC Burst Mode
Normal Operating
VFB ＜ VG, TA = 25°C
VFB ＞ VFB-OLP,
TA = 25°C
VDD = 25V
VDD = 15V, IO = 100mA
VDD = 15V, IO = 100mA
CL = 3nF, VDD = 12V,
20~80%
CL = 3nF, VDD = 12V,
20~80%
IDET ＜ 75µA, TA = 25°C
IDET = 185µA, TA = 25°C
IDET = 350µA, TA = 25°C
IDET = 550µA, TA = 25°C
tON = 45µs,
RANGE = Open
tON = 0µs
CSPWM Pin Floating
CSPWM Pin Floating
Min.
1.65
1.60
Typ.
1.70
1.65
Max.
1.75
1.70
Units
V
1.75 1.80
1.85
V
100 ms
200 µs
1.85 2.25 2.65 ms
22 28
34 µs
16.0 17.5
8
80
40
19.0
1.5
110
70
V
V
V
ns
ns
150
0.81 0.84
0.69 0.72
0.55 0.58
0.37 0.40
200
0.87
0.75
0.61
0.43
ns
V
0.25 0.30
0.05 0.10
300
0.35
0.15
V
ns
4.5 5.0 V
150 µs
Continued on the following page…
www.DataSheet4U.com
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.3
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet FAN6920MR.PDF ] | |
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