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PDF FAN6921ML Data sheet ( Hoja de datos )

Número de pieza FAN6921ML
Descripción Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! FAN6921ML Hoja de datos, Descripción, Manual

June 2010
FAN6921ML
Integrated Critical Mode PFC/Quasi-Resonant
Current Mode PWM Controller
Features
ƒ Integrated PFC and Flyback Controller
ƒ Critical Mode PFC Controller
ƒ Zero-Current Detection for PFC Stage
ƒ Quasi-Resonant Operation for PWM Stage
ƒ Internal Minimum toff 8µs for QR PWM Stage
ƒ Internal 10ms Soft-Start for PWM
ƒ Brownout Protection
ƒ H/L Line Over-Power Compensation (OPC)
ƒ Latched Protection (FB Pin)
Over-Power/ Overload Protection
Short-Circuit Protection
Open-Loop Protection
ƒ Externally Latch Triggering (RT Pin)
ƒ Adjustable Over-Temperature Latched (RT Pin)
ƒ VDD Pin & Output Voltage OVP (Latched)
ƒ Internal Temperature Shutdown (140°C)
Applications
ƒ AC/DC NB Adapters
ƒ Open-Frame SMPS
ƒ Battery Charger
Description
The highly integrated FAN6921ML combines a Power
Factor Correction (PFC) controller and a Quasi-
Resonant PWM controller. Integration provides cost-
effect design and allows for fewer external components.
For PFC, FAN6921ML uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power factor correction. With an
innovative THD optimizer, FAN6921ML can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6921ML enhances the power system
performance through valley detection, green-mode
operation, and high / low line over power compensation.
FAN6921ML provides: secondary-side open-loop and
over-current protection, external latch triggering,
adjustable over-temperature protection by RT pin and
external NTC resistor, internal over-temperature
shutdown, VDD pin OVP, and DET pin over-voltage for
output OVP, and brownin/out for AC input voltage
under-voltage protection (UVP).
The FAN6921ML controller is available in a 16-pin small
outline package (SOP).
Ordering Information
www.DataSheet4U.com
Part Number
OLP Mode
Operating
Temperature Range
Package
FAN6921MLMY
Latch
-40°C to +105°C 16-Pin Small Outline Package (SOP)
Packing
Method
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
www.fairchildsemi.com

1 page




FAN6921ML pdf
Pin Definitions
Pin # Name Description
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
5 CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
during PWM on time.
6
OPFC
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is
15.5V.
7
VDD
Power supply. The threshold voltages for startup and turn-off are 18V and 7.5V, respectively. The
startup current is less than 30µA and the operating current is lower than 10mA.
8
OPWM
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5V.
9 GND The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
ƒ Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
10
DET
ƒ Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
ƒ Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5V, the controller enters latch mode and stops all PFC
and PWM switching operation.
Feedback voltage pin. This pin is used to receive the output voltage level signal to determine PWM
gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, overload,
11 FB or output-short-circuit protection if the FB pin voltage is higher than a threshold of around 4.2V for
more than 50ms.The input impedance of this pin is a 5kequivalent resistance. A 1/3 attenuator is
connected between the FB pin and the input of the CSPWM/FB comparator.
Adjustable over-temperature protection and external latch triggering. A constant current flows out
12 RT of the RT pin. When RT pin voltage is lower than 0.8V (typical), latch mode protection is activated
and stops all PFC and PWM switching operation until the AC plug is removed.
Line-voltage detection for brownin/out protections. This pin can receive the AC input voltage level
13 VIN through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s
status, but it can also perform brownin/out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
14
ZCD
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle.
When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and the
controller stops PFC switching. This can be realized with an external circuit if disabling the PFC
stage is desired.
15 NC No connection
16
HV
High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100ktypical)
for providing a high-charging current to VDD capacitor.
www.DataSheet4U.com
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
5
www.fairchildsemi.com

5 Page





FAN6921ML arduino
Electrical Characteristics (Continued)
VDD=15V, TA=-40~105(TA=TJ), unless otherwise specified.
Symbol
Parameter
Conditions
PWM Output Section
VCLAMP
PWM Gate Output Clamping
Voltage
VDD= 25V
VOL PWM Gate Output Voltage Low VDD= 15V, Io=100mA
VOH PWM Gate Output Voltage High VDD= 15V, Io=100mA
tR
PWM Gate Output Rising Time
CL=3nF,
VDD=12V, 20~80%
tF
PWM Gate Output Falling Time
CL=3nF,
VDD=12V, 20~80%
Current Sense Section
tPD
VLIMIT
VSLOPE
Delay to Output
The Limit Voltage on CSPWM
Pin for Over Power
Compensation
Slope Compensation(4)
IDET < 75µA, TA=25°C
IDET=185µA, TA=25°C
IDET=350µA, TA=25°C
IDET=550µA, TA=25°C
tON=45µs,
RANGE=Open
tON=0µs
tON-BNK Leading-Edge Blanking Time
VCS-FLOATING
CSPWM Pin Floating VCSPWM
Clamped High Voltage
CSPWM Pin Floating
tCS-H Delay Once CSPWM Pin Floating CSPWM Pin Floating
RT Pin Over-Temperature Protection Section
TOTP
Internal Threshold Temperature
for OTP(4)
TOTP-HYST
Hysteresis Temperature for
Internal OTP(4)
IRT Internal Source Current of RT Pin
VRT-LATCH Latch-Mode Triggering Voltage
VRT-RE-LATCH Latch-Mode Release Voltage
VRT-OTP-LEVEL
Threshold Voltage for Two-level
Debounce Time
tRT-OTP-H
tRT-OTP-L
Debounce Time for OTP
Debounce Time for Externally
Triggering
Note:
4. Guaranteed by design.
www.DataSheet4U.com
VRT<VRT-OTP-LEVEL
Min. Typ. Max.
16.0
17.5
8
80
40
19.0
1.5
110
70
0.81
0.69
0.55
0.37
0.25
0.05
4.5
150
0.84
0.72
0.58
0.40
0.30
0.10
300
150
200
0.87
0.75
0.61
0.43
0.35
0.15
5
125 140
155
30
90
0.75
VRT-LATCH
+0.15
100
0.80
VRT-LATCH
+0.20
110
0.85
VRT-LATCH
+0.25
0.45 0.50
0.55
10
70 100 130
Units
V
V
V
ns
ns
ns
V
V
ns
V
µs
°C
°C
µA
V
V
V
ms
µs
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
11
www.fairchildsemi.com

11 Page







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