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PDF KSZ8895FMQ Data sheet ( Hoja de datos )
| Número de pieza | KSZ8895FMQ | |
| Descripción | Integrated 5-Port 10/100 Managed Ethernet Switch | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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KSZ8895MQ/RQ/FMQ
Integrated 5-Port 10/100 Managed Ethernet
Switch with MII/RMII interface
Rev. 1.2
General Description
The KSZ8895MQ/RQ/FMQ is a highly-integrated Layer
2 managed five-port switch with optimized design and
plentiful features. It is designed for cost-sensitive
10/100Mbps five-port switch systems with lowest power
consumption, on-chip termination and internal core
power controller. These features will save more system
cost. It supports high-performance memory bandwidth,
shared memory based switch fabric with non-blocking
configuration. It also provides an extensive feature set
such as power management, programmable rate limit
and priority ratio, tag/port-based VLAN, packets filtering,
four queues QoS prioritization, management interfaces
and MIB counters. KSZ8895 family provides multiple
CPU data interfaces to effectively address both current
and emerging fast Ethernet applications when port 5 is
configured to separate MAC5 with SW5-MII/RMII and
PHY5 with P5-MII/RMII interfaces.
The configurations provided by the KSZ8895 family
enables the flexibility to meet different requirements:
• KSZ8895MQ: Five 10/100Base-T/TX transceivers,
one SW5-MII and one P5-MII interface
• KSZ8895RQ: Five 10/100Base-T/TX transceivers,
one SW5-RMII and one P5-RMII interface
• KSZ8895FMQ: Three 10/100Base-T/TX transceiver
on Ports 1, 2, 5 and two 100Base-FX transceivers
on Ports 3, 4, one SW5-MII and one P5-MII
interface
All registers of MACs and PHYs units can be managed
by the SPI or the SMI interface. MIIM registers can be
accessed through the MDC/MDIO interface. EEPROM
can set all control registers for the unmanaged mode.
Functional Diagram
www.DataSheet4U.com
Note: SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port 5.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 2011
M9999-012011-1.2
1 page  
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
Port 5 PHY 5 P5-MII/RMII Interface............................................................................................................................37
Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ ......................................................................................38
Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ .................................................................................39
SNI Interface Operation ..............................................................................................................................................41
Advanced Functionality................................................................................................................................................42
QoS Priority Support ...................................................................................................................................................42
Port-Based Priority..................................................................................................................................................42
802.1p-Based Priority .............................................................................................................................................42
DiffServ-Based Priority ...........................................................................................................................................43
Spanning Tree Support...............................................................................................................................................43
Rapid Spanning Tree Support ....................................................................................................................................44
Tail Tagging Mode ......................................................................................................................................................45
IGMP Support .............................................................................................................................................................46
Port Mirroring Support ................................................................................................................................................46
VLAN Support .............................................................................................................................................................46
Rate Limiting Support .................................................................................................................................................47
Ingress Rate Limit...................................................................................................................................................47
Egress Rate Limit ...................................................................................................................................................48
Transmit Queue Ratio Programming......................................................................................................................48
Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast ..................48
Configuration Interface ...............................................................................................................................................48
I2C Master Serial Bus Configuration .......................................................................................................................48
SPI Slave Serial Bus Configuration ........................................................................................................................49
MII Management Interface (MIIM) ..........................................................................................................................52
Serial Management Interface (SMI)........................................................................................................................52
Register Description .....................................................................................................................................................54
Global Registers .........................................................................................................................................................56
Register 0 (0x00): Chip ID0 ....................................................................................................................................56
Register 1 (0x01): Chip ID1 / Start Switch..............................................................................................................56
Register 2 (0x02): Global Control 0 ........................................................................................................................56
Register 3 (0x03): Global Control 1 ........................................................................................................................57
Register 4 (0x04): Global Control 2 ........................................................................................................................58
Register 5 (0x05): Global Control 3 ........................................................................................................................59
Register 6 (0x07): Global Control 4 ........................................................................................................................60
Register 7 (0x07): Global Control 5 ........................................................................................................................60
Register 8 (0x08): Global Control 6 ........................................................................................................................60
Register 9 (0x09): Global Control 7 ........................................................................................................................61
Register 10 (0x0A): Global Control 8......................................................................................................................62
Register 11 (0x0B): Global Control 9......................................................................................................................62
Register 12 (0x0C): Global Control 10 ...................................................................................................................63
www.DataRSheegeist4tUer.c1o3m(0x0D): Global Control 11 ...................................................................................................................63
Register 14 (0x0E): Power Down Management Control 1 .....................................................................................63
Register 15 (0x0F): Power Down Management Control 2....................................... Error! Bookmark not defined.
Port Registers .............................................................................................................................................................65
January 2011
5 M9999-012011-1.2
5 Page 
Micrel, Inc.
KSZ8895MQ/RQ/FMQ
List of Figures
Figure 1. Typical Straight Cable Connection ............................................................................................................... 27
Figure 2. Typical Crossover Cable Connection ........................................................................................................... 28
Figure 3. Auto-Negotiation ........................................................................................................................................... 29
Figure 4. Destination Address Lookup Flow Chart, Stage 1 ........................................................................................ 34
Figure 5. Destination Address Resolution Flow Chart, Stage 2................................................................................... 35
Figure 6. 802.1p Priority Field Format.......................................................................................................................... 42
Figure 7. Tail Tag Frame Format .................................................................................................................................. 45
Figure 8. KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram ................................................................ 49
Figure 9. SPI Write Data Cycle .................................................................................................................................... 50
Figure 10. SPI Read Data Cycle .................................................................................................................................. 50
Figure 11. SPI Multiple Write ....................................................................................................................................... 51
Figure 12. SPI Multiple Read ....................................................................................................................................... 51
Figure 13. EEPROM Interface Input Receive Timing Diagram.................................................................................. 102
Figure 14. EEPROM Interface Output Transmit Timing Diagram .............................................................................. 102
Figure 15. SNI Input Timing ....................................................................................................................................... 103
Figure 16. SNI Output Timing .................................................................................................................................... 103
Figure 17. MAC Mode MII Timing – Data Received from MII .................................................................................... 104
Figure 18. MAC Mode MII Timing – Data Transmitted from MII ................................................................................ 104
Figure 19. PHY Mode MII Timing – Data Received from MII..................................................................................... 105
Figure 20. PHY Mode MII Timing – Data Transmitted from MII................................................................................. 105
Figure 21. RMII Timing – Data Received from RMII .................................................................................................. 106
Figure 22. RMII Timing – Data Transmitted to RMII .................................................................................................. 106
Figure 23. SPI Input Timing ....................................................................................................................................... 107
Figure 24. SPI Output Timing..................................................................................................................................... 108
Figure 25: Auto-Negotiation Timing ........................................................................................................................... 109
Figure 26. MDC/MDIO Timing.................................................................................................................................... 110
Figure 27. Reset Timing ............................................................................................................................................. 111
Figure 28. Recommended Reset Circuit .................................................................................................................... 112
Figure 29. Recommended Circuit for Interfacing with CPU/FPGA Reset.................................................................. 112
www.DataSheet4U.com
January 2011
11 M9999-012011-1.2
11 Page | ||
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