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PDF KSZ8862-16MQL Data sheet ( Hoja de datos )

Número de pieza KSZ8862-16MQL
Descripción 2-Port Ethernet Switch
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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KSZ8862-16/32MQL
2-Port Ethernet Switch with Non-PCI Interface
and Fiber Support
Rev 3.1
General Description
The KSZ8862M is 2-port switch with non-PCI CPU
interface and fiber support, and is available in 8/16-bit
and 32-bit bus designs (see Ordering Information). This
datasheet describes the KSZ8862M non-PCI CPU
interface chip.
The KSZ8862M is the industry’s first fully managed, 2-
port switch with a non-PCI CPU interface and fiber
support. It is based on a proven, 4th generation,
integrated Layer-2 switch, compliant with IEEE 802.3u
standards.
For industrial applications, the KSZ8862M can run in
half-duplex mode regardless of the application.
In fiber mode, port 1 can be configurable to either
100BASE-FX or 100BASE-SX/10BASE-FL.
The LED driver and post amplifier are also included for
10Base-FL and 100Base-SX applications.
Functional Diagram
LinkMD®
In copper mode, port 2 supports 10/100BASE-T/TX with
HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
Micrel’s proprietary LinkMD® Time Domain
Reflectometry (TDR)-based function is also available for
determining the cable length, as well as cable
diagnostics for identifying faulty cabling.
The KSZ8862M offers an extensive feature set that
includes tag/port-based VLAN, quality of service (QoS)
priority management, management information base
(MIB) counters, and CPU control/data interfaces to
effectively address Fast Ethernet applications.
The KSZ8862M contains: Two 10/100 transceivers with
patented, mixed-signal, low-power technology, two
media access control (MAC) units, a direct memory
access (DMA) channel, a high-speed, non-blocking,
switch fabric, a dedicated 1K entry forwarding table, and
an on-chip frame buffer memory.
P ort 1
F ib e r
TX
RX
P o rt 2
Copper
LED
D riv e r
Post
Am p
1 0 /1 0 0 B a s e -
F L /F X /S X
PHY 1
1 0 /1 0 0
MAC 1
1 0 /1 0 0 B a s e -
T /T X
PHY 2
1 0 /1 0 0
MAC 2
Em bedded
P ro c e s s o r In te rfa c e
N o n -P C I
CPU
Bus
In te rfa c e
U n it
QMU
DM A
C h ann el
8 ,1 6 , o r 3 2 -b it
G en eric H o st
In te rfa c e
P 1 L E D [3:0]
P 2 L E D [3:0]
www.DataSheet4U.com E E P R O M I/F
LED
D rivers
RXQ
4K B
TXQ
4K B
C o n tro l
R eg iste rs
S w itc h
H ost
MAC
1 K lo o k -u p
E n g in e
S c h e d u lin g
M anagem ent
B u ffer
M anagem ent
F ram e
B u ffe rs
M IB
C o unters
EEPRO M
In te rfa ce
Figure 1. KSZ8862M Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2010
M9999-081310-3.1

1 page




KSZ8862-16MQL pdf
Micrel, Inc.
KSZ8862-16/32MQL
Inter Packet Gap (IPG) ............................................................................................................................................................ 32
Back-Off Algorithm................................................................................................................................................................... 32
Late Collision ........................................................................................................................................................................... 32
Legal Packet Size .................................................................................................................................................................... 32
Flow Control............................................................................................................................................................................. 32
Half-Duplex Backpressure ....................................................................................................................................................... 32
Broadcast Storm Protection ..................................................................................................................................................... 33
Clock Generator....................................................................................................................................................................... 33
Bus Interface Unit (BIU)................................................................................................................................................33
Asynchronous Interface ........................................................................................................................................................... 35
Synchronous Interface ............................................................................................................................................................. 36
Summary.................................................................................................................................................................................. 36
BIU Implementation Principles ................................................................................................................................................. 37
Queue Management Unit (QMU) ..................................................................................................................................38
Transmit Queue (TXQ) Frame Format..................................................................................................................................... 38
Receive Queue (RXQ) Frame Format ..................................................................................................................................... 39
Advanced Switch Functions ........................................................................................................................................41
Spanning Tree Support............................................................................................................................................................ 41
IGMP Support .......................................................................................................................................................................... 42
“IGMP” Snooping................................................................................................................................................................... 42
“Multicast Address Insertion” in the Static MAC Table........................................................................................................... 42
IPv6 MLD Snooping ................................................................................................................................................................. 42
Port Mirroring Support.............................................................................................................................................................. 42
IEEE 802.1Q VLAN Support .................................................................................................................................................... 43
QoS Priority Support ................................................................................................................................................................ 43
Port-Based Priority................................................................................................................................................................... 43
802.1p-Based Priority .............................................................................................................................................................. 43
DiffServ-Based Priority............................................................................................................................................................. 44
Rate Limiting Support .............................................................................................................................................................. 44
MAC Filtering Function ............................................................................................................................................................ 45
Configuration Interface............................................................................................................................................................. 45
EEPROM Interface .................................................................................................................................................................. 45
Loopback Support.................................................................................................................................................................... 46
Far-end Loopback ............................................................................................................................................................... 46
Near-end (Remote) Loopback............................................................................................................................................. 46
CPU Interface I/O Registers .........................................................................................................................................48
I/O Registers ............................................................................................................................................................................ 48
Internal I/O Space Mapping ..................................................................................................................................................... 49
Register Map: Switch and MAC/PHY...........................................................................................................................57
Bit Type Definition.................................................................................................................................................................... 57
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)............................................................................. 57
Bank 0 Base Address Register (0x00): BAR............................................................................................................................ 57
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ........................................................ 57
Bank 0 Bus Error Status Register (0x06): BESR ..................................................................................................................... 58
Bank 0 Bus Burst Length Register (0x08): BBLR..................................................................................................................... 58
Bank 1 Reserved ..................................................................................................................................................................... 58
www.DBataanSkhe2eHt4oUs.tcMomAC Address Register Low (0x00): MARL ......................................................................................................... 58
Bank 2 Host MAC Address Register Middle (0x02): MARM..................................................................................................... 59
Bank 2 Host MAC Address Register High (0x04): MARH ........................................................................................................ 59
Bank 3 On-Chip Bus Control Register (0x00): OBCR .............................................................................................................. 59
Bank 3 EEPROM Control Register (0x02): EEPCR ................................................................................................................. 60
Bank 3 Memory BIST INFO Register (0x04): MBIR ................................................................................................................. 60
August 2010
5 M9999-081310-3.1

5 Page





KSZ8862-16MQL arduino
Micrel, Inc.
Pin Configuration for KSZ8862-16MQL (8/16-Bit)
KSZ8862-16/32MQL
Figure 2. 128-Pin PQFP
(Top View)
www.DataSheet4U.com
August 2010
11 M9999-081310-3.1

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