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PDF KSZ8842-32MVL Data sheet ( Hoja de datos )

Número de pieza KSZ8842-32MVL
Descripción 2-Port Ethernet Switch
Fabricantes Micrel Semiconductor 
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KSZ8842-16/32
MQL/MVL/MVLI/MBL
2-Port Ethernet Switch with Non-PCI Interface
Data Sheet Rev 1.9
General Description
The KSZ8842-series of 2-port switches includes PCI and
non-PCI CPU interfaces, and are available in 8/16-bit
and 32-bit bus designs (see Ordering Information).
This datasheet describes the KSZ8842M-series of non-
PCI CPU interface chips. For information on the
KSZ8842 PCI CPU interface switches, refer to the
KSZ8842P datasheet.
The KSZ8842M is the industry’s first fully managed, 2-
port switch with a non-PCI CPU interface. It is based on
a proven, 4th generation, integrated Layer-2 switch,
compliant with IEEE 802.3u standards. Also an industrial
temperature grade version of the KSZ8842, the
KSZ8842MVLI, can be ordered (see Ordering
Information).
The KSZ8842M can be configured as a switch or as a
low-latency (310 nanoseconds) repeater in latency-
critical, embedded or industrial Ethernet applications.
For industrial applications, the KSZ8842M can run in
half-duplex mode regardless of the application.
Functional Diagram
LinkMD®
The KSZ8842M offers an extensive feature set that
includes tag/port-based VLAN, quality of service (QoS)
priority management, management information base
(MIB) counters, and CPU control/data interfaces to
effectively address Fast Ethernet applications.
The KSZ8842M contains: Two 10/100 transceivers with
patented, mixed-signal, low-power technology, two
media access control (MAC) units, a direct memory
access (DMA) channel, a high-speed, non-blocking,
switch fabric, a dedicated 1K entry forwarding table, and
an on-chip frame buffer memory.
P 1 H P A u to
M D I/M D I-X
P 2 H P A u to
M D I/M D I-X
10 /10 0 B ase -
T /T X
PHY 1
10 /10 0 B ase -
T /T X
PHY 2
10 /1 00
MAC 1
10 /1 00
MAC 2
Em bedded
P ro ce ss o r In te rfa c e
N on-P C I
CPU
Bus
In te rfa c e
U nit
QMU
DMA
C hannel
8 ,1 6 , o r 3 2 -b it
G en eric H o st
In te rface
P 1 L E D [3 :0 ]
P 2 L E D [3 :0 ]
www.DataSheet4U.com
E E P R O M I/F
LED
D rive rs
RXQ
4KB
TXQ
4KB
C on trol
R e g is te rs
S w itc h
H ost
MAC
1 K lo o k -u p
E n g in e
S c h e d u lin g
M anagem ent
B uffe r
M anagem ent
F ram e
B u ffers
M IB
C ou nte rs
EEPROM
Inte rface
Figure 1. KSZ8842M Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies
October 2007
1
M9999-102207-1.9

1 page




KSZ8842-32MVL pdf
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
“Multicast Address Insertion” in the Static MAC Table ......................................................................................................45
IPv6 MLD Snooping...............................................................................................................................................................45
Port Mirroring Support ...........................................................................................................................................................45
IEEE 802.1Q VLAN Support..................................................................................................................................................45
QoS Priority Support..............................................................................................................................................................46
Port-Based Priority.................................................................................................................................................................46
802.1p-Based Priority ............................................................................................................................................................46
DiffServ based Priority ...........................................................................................................................................................47
Rate Limiting Support ............................................................................................................................................................47
MAC Filtering Function ..........................................................................................................................................................48
Configuration Interface ..........................................................................................................................................................48
EEPROM Interface ................................................................................................................................................................48
Loopback Support .................................................................................................................................................................49
Far-end Loopback.............................................................................................................................................................49
Near-end (Remote) Loopback ..........................................................................................................................................49
CPU Interface I/O Registers .................................................................................................................................. 51
I/O Registers..........................................................................................................................................................................51
Internal I/O Space Mapping ...................................................................................................................................................52
Register Map: Switch & MAC/PHY ....................................................................................................................... 60
Bit Type Definition .................................................................................................................................................................60
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) ..........................................................................60
Bank 0 Base Address Register (0x00): BAR .........................................................................................................................60
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ......................................................61
Bank 0 Bus Error Status Register (0x06): BESR ...................................................................................................................61
Bank 0 Bus Burst Length Register (0x08): BBLR ..................................................................................................................61
Bank 1: Reserved ..................................................................................................................................................................62
Bank 2 Host MAC Address Register Low (0x00): MARL .......................................................................................................62
Bank 2 Host MAC Address Register Middle (0x02): MARM ..................................................................................................62
Bank 2 Host MAC Address Register High (0x04): MARH......................................................................................................62
Bank 3 On-Chip Bus Control Register (0x00): OBCR............................................................................................................63
Bank 3 EEPROM Control Register (0x02): EEPCR...............................................................................................................63
Bank 3 Memory BIST INFO Register (0x04): MBIR...............................................................................................................64
Bank 3 Global Reset Register (0x06): GRR ..........................................................................................................................64
Bank 3 Bus Configuration Register (0x08): BCFG.................................................................................................................64
Banks 4 – 15: Reserved ........................................................................................................................................................64
Bank 16 Transmit Control Register (0x00): TXCR .................................................................................................................65
Bank 16 Transmit Status Register (0x02): TXSR ..................................................................................................................65
Bank 16 Receive Control Register (0x04): RXCR .................................................................................................................65
Bank 16 TXQ Memory Information Register (0x08): TXMIR..................................................................................................66
Bank 16 RXQ Memory Information Register (0x0A): RXMIR.................................................................................................66
Bank 17 TXQ Command Register (0x00): TXQCR................................................................................................................67
Bank 17 RXQ Command Register (0x02): RXQCR ...............................................................................................................67
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR ..................................................................................................67
Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR .................................................................................................68
Bank 17 QMU Data Register Low (0x08): QDRL...................................................................................................................68
Bank 17 QMU Data Register High (0x0A): QDRH .................................................................................................................68
Bank 18 Interrupt Enable Register (0x00): IER......................................................................................................................69
wwwB.Danakta1S8heInette4rUru.cpotmStatus Register (0x02): ISR.......................................................................................................................70
Bank 18 Receive Status Register (0x04): RXSR ...................................................................................................................71
Bank 18 Receive Byte Counter Register (0x06): RXBC ........................................................................................................72
Bank 19 Multicast Table Register 0 (0x00): MTR0 ................................................................................................................72
Bank 19 Multicast Table Register 1 (0x02): MTR1 ................................................................................................................72
Bank 19 Multicast Table Register 2 (0x04): MTR2 ................................................................................................................72
October 2007
5
M9999-102207-1.9

5 Page





KSZ8842-32MVL arduino
Micrel, Inc.
Pin Configuration for KSZ8842-16 Switches (8/16-Bit)
KSZ8842-16/32 MQL/MVL/MVLI/MBL
NC
NC
NC
NC
DGND
V D D IO
NC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
DGND
DGND
V D D IO
D2
D1
D0
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
K S Z 8 8 4 2 -1 6
MQL
(Top View)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AGND
VDDAP
AGND
IS E T
NC
NC
AGND
VDDA
TXP2
TXM2
AGND
RXP2
RXM2
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
NC
VDDA
AGND
NC
NC
AGND
Figure 2. Standard – KSZ8842-16 MQL 128-Pin PQFP (Top View)
www.DataSheet4U.com
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DGND
V D D IO
NC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
DGND
DGND
V D D IO
D2
D1
D0
97 64
98 63
99 62
100 61
101
102
103
60
59
K S Z 8 842-16104
105
106
107
108
109
110
58
57
56
55
54
53
52
111
112
M V L113
114
115
116
117
118
119
120
(Top View)
121
122
123
51
50
49
48
47
46
45
44
43
42
41
40
39
124 38
125
126
127
37
36
35
128
34
33
AGND
VDDAP
AGND
IS E T
NC
NC
AGND
VDDA
TXP2
TXM2
AGND
RXP2
RXM2
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
NC
VDDA
AGND
NC
NC
AGND
VDDA
AGND
PWRDN
ADSN
DGND
WRN
Figure 3. Option – KSZ8842-16 MVL 128-Pin LQFP (Top View)
October 2007
11
M9999-102207-1.9

11 Page







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