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PDF KSZ8841-16MQL Data sheet ( Hoja de datos )

Número de pieza KSZ8841-16MQL
Descripción Single-Port Ethernet MAC Controller
Fabricantes Micrel Semiconductor 
Logotipo Micrel Semiconductor Logotipo



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KSZ8841-16/32MQL/MVL/MVLI/MBL
Single-Port Ethernet MAC Controller
with Non-PCI Interface
Rev. 1.6
General Description
The KSZ8841-series single-port chip includes PCI and
non-PCI CPU interfaces, and are available in 8/16-bit and
32-bit bus designs. This datasheet describes the
KSZ8841M-series of non-PCI CPU interface chips. For
information on the KSZ8841 PCI CPU interface chips,
refer to the KSZ8841P datasheet.
The KSZ8841M is a single chip, mixed analog/digital
device offering Wake-on-LAN technology for effectively
addressing Fast Ethernet applications. It consists of a Fast
Ethernet MAC controller, an 8-bit, 16-bit, and 32-bit
generic host processor interface and incorporates a unique
dynamic memory pointer with 4-byte buffer boundary and
a fully utilizable 8KB for both TX and RX directions in host
buffer interface.
The KSZ8841M is designed to be fully compliant with the
appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8841M, the
KSZ8841MVLI, also can be ordered (see “Ordering
Information section).
LinkMD®
Physical signal transmission and reception are enhanced
through the use of analog circuitry, making the design
more efficient and allowing for lower-power consumption.
The KSZ8841M is designed using a low-power CMOS
process that features a single 3.3V power supply with 5V
tolerant I/O. It has an extensive feature set that offers
management information base (MIB) counters and CPU
control/data interfaces.
The KSZ8841M includes a unique cable diagnostics
feature called LinkMD®. This feature determines the length
of the cabling plant and also ascertains if there is an open
or short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8841M
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Functional Diagram
P 1 H P A u to
M D I/M D I-X
1 0 /1 0 0
B a s e -T /T X
PHY
H ost M AC
E m b e d d e d P ro ce sso r
In te rfa c e
8 ,1 6 , o r 3 2 -b it G e n e ric
H o s t In te rfa c e
N o n -P C I
CPU
B us
In te rfa c e
U n it
QMU
DMA
C hannel
P 1 L E D [3 :0 ]
www.DataSheet4U.com E E P R O M I / F
LE D
D riv e r
RXQ
4KB
TXQ
4KB
C o n tro l
R e g is te rs
M IB
C o u n te rs
EEPR O M
In te rfa c e
Figure 1. KSZ8841M Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
Product names used in this datasheet are for identification purposes
only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2007
M9999-102207-1.6

1 page




KSZ8841-16MQL pdf
Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Receive Queue (RXQ) Frame Format........................................................................................................................................ 39
EEPROM Interface ....................................................................................................................................................... 40
Loopback Support ........................................................................................................................................................ 42
Near-end (Remote) Loopback.................................................................................................................................................... 42
CPU Interface I/O Registers ............................................................................................................................................... 43
I/O Registers .............................................................................................................................................................................. 43
Internal I/O Space Mapping ....................................................................................................................................................... 44
Register Map: MAC and PHY ............................................................................................................................................. 52
Bit Type Definition ........................................................................................................................................................ 52
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) ................................................................ 52
Bank 0 Base Address Register (0x00): BAR................................................................................................................ 52
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR ........................................... 53
Bank 0 Bus Error Status Register (0x06): BESR ......................................................................................................... 53
Bank 0 Bus Burst Length Register (0x08): BBLR......................................................................................................... 53
Bank 1: Reserved ......................................................................................................................................................... 53
Bank 2 Host MAC Address Register Low (0x00): MARL ............................................................................................. 54
Bank 2 Host MAC Address Register Middle (0x02): MARM ........................................................................................ 54
Bank 2 Host MAC Address Register High (0x04): MARH............................................................................................ 54
Bank 3 On-Chip Bus Control Register (0x00): OBCR .................................................................................................. 55
Bank 3 EEPROM Control Register (0x02): EEPCR ..................................................................................................... 55
Bank 3 Memory BIST Info Register (0x04): MBIR........................................................................................................ 56
Bank 3 Global Reset Register (0x06): GRR................................................................................................................. 56
Bank 3 Power Management Capabilities Register (0x08): PMCR ............................................................................... 56
Bank 3 Wakeup Frame Control Register (0x0A): WFCR ............................................................................................. 57
Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0...................................................................................... 58
Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1...................................................................................... 58
Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0 .............................................................................. 58
Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1 .............................................................................. 58
Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2 .............................................................................. 58
Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3.............................................................................. 59
Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0...................................................................................... 59
Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1...................................................................................... 59
Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0 .............................................................................. 59
Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1 .............................................................................. 59
Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2 .............................................................................. 60
Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3.............................................................................. 60
Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0...................................................................................... 60
Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1...................................................................................... 60
Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0 .............................................................................. 60
Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1 .............................................................................. 61
Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2 .............................................................................. 61
Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3.............................................................................. 61
Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0...................................................................................... 61
Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1...................................................................................... 61
Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0 .............................................................................. 62
Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1 .............................................................................. 62
www.DBBataaannShkke77etWW4Uaa.ckkoeemuupp
Frame
Frame
3
3
Byte
Byte
Mask
Mask
2
3
Register
Register
(0x08):
(0x0A):
WF3BM2 ..............................................................................
WF3BM3..............................................................................
62
62
Bank 8 – 15: Reserved ................................................................................................................................................. 62
Bank 16 Transmit Control Register (0x00): TXCR ....................................................................................................... 63
Bank 16 Transmit Status Register (0x02): TXSR......................................................................................................... 63
Bank 16 Receive Control Register (0x04): RXCR........................................................................................................ 64
Bank 16 TXQ Memory Information Register (0x08): TXMIR........................................................................................ 64
October 2007
5 M9999-102207-1.6

5 Page





KSZ8841-16MQL arduino
Micrel, Inc.
Ball Configuration for KSZ8841-16 Chip (8/16-Bit)
KSZ8841-16/32 MQL/MVL/MBL
Figure 4. KSZ8841-16MBL 100-Ball LFBGA (Top View)
www.DataSheet4U.com
October 2007
11 M9999-102207-1.6

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