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PDF KS8995XA Data sheet ( Hoja de datos )

Número de pieza KS8995XA
Descripción Integrated 5-Port 10/100 QoS Switch
Fabricantes Micrel Semiconductor 
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KS8995XA
Integrated 5-Port 10/100 QoS Switch
Rev 2.6
General Description
The KS8995XA is a highly integrated Layer-2 quality of
service (QoS) switch with optimized bill of materials
(BOM) cost for low port count, cost-sensitive
10/100Mbps switch systems. It also provides an
extensive feature set including three different QoS
priority schemes, a dual MII interface for BOM cost
reduction, rate limiting to offload CPU tasks, software
and hardware power-down, a MDC/MDIO control
interface and port mirroring/monitoring to effectively
address both current and emerging Fast Ethernet
applications.
The KS8995XA contains five 10/100 transceivers with
patented mixed-signal low-power technology, five media
access control (MAC) units, a high-speed non-blocking
switch fabric, a dedicated address lookup engine, and
an on-chip frame buffer memory.
All PHY units support 10BASE-T and 100BASE-TX. In
addition, two of the PHY units support 100BaseFX
(Ports 4 and 5).
Functional Diagram
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
Auto
MDI/MDI-X
MII-P5
MDC, MDI/O
MII-SW or SNI
LED0[5:1]
LED1[5:1]
LED2[5:1]
www.DataSheet4U.com
10/100
T/Tx 1
10/100
T/Tx 2
10/100
T/Tx 3
10/100
T/Tx/Fx 4
10/100
T/Tx/Fx 5
10/100
MAC 1
10/100
MAC 2
10/100
MAC 3
10/100
MAC 4
10/100
MAC 5
SNI
LED I/F
Control
Registers
KS8995XA
1K Look-Up
Engine
Queue
Mgmnt
Buffer
Mgmnt
Frame
Buffers
EEPROM
I/F
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
September 2008
M9999-091508

1 page




KS8995XA pdf
Micrel, Inc.
KS8995XA
Register 11 (0x0B): Global Control 9........................................................................................................................ 34
Port Registers ........................................................................................................................................................... 35
Register 16 (0x10): Port 1 Control 0 ......................................................................................................................... 35
Register 17 (0x11): Port 1 Control 1 ......................................................................................................................... 35
Register 18 (0x12): Port 1 Control 2 ......................................................................................................................... 36
Register 19 (0x13): Port 1 Control 3 ......................................................................................................................... 37
Register 20 (0x14): Port 1 Control 4 ......................................................................................................................... 37
Register 21 (0x15): Port 1 Control 5 ......................................................................................................................... 37
Register 22 (0x16): Port 1 Control 6 ......................................................................................................................... 37
Register 23 (0x17): Port 1 Control 7 ......................................................................................................................... 38
Register 24 (0x18): Port 1 Control 8 ......................................................................................................................... 38
Register 25 (0x19): Port 1 Control 9 ......................................................................................................................... 38
Register 26 (0x1A): Port 1 Control 10....................................................................................................................... 39
Register 27 (0x1B): Port 1 Control 11....................................................................................................................... 39
Register 28 (0x1C): Port 1 Control 12 ...................................................................................................................... 40
Register 29 (0x1D): Port 1 Control 13 ...................................................................................................................... 40
Register 30 (0x1E): Port 1 Status 0 .......................................................................................................................... 41
Register 31 (0x1F): Port 1 Control 14....................................................................................................................... 41
Advanced Control Registers ..................................................................................................................................... 43
Register 96 (0x60): TOS Priority Control Register 0 ................................................................................................ 43
Register 97 (0x61): TOS Priority Control Register 1 ................................................................................................ 43
Register 98 (0x62): TOS Priority Control Register 2 ................................................................................................ 43
Register 99 (0x63): TOS Priority Control Register 3 ................................................................................................ 43
Register 100 (0x64): TOS Priority Control Register 4 .............................................................................................. 43
Register 101 (0x65): TOS Priority Control Register 5 .............................................................................................. 43
Register 102 (0x66): TOS Priority Control Register 6 .............................................................................................. 43
Register 103 (0x67): TOS Priority Control Register 7 .............................................................................................. 43
Register 104 (0x68): MAC Address Register 0......................................................................................................... 43
Register 105 (0x69): MAC Address Register 1......................................................................................................... 43
Register 106 (0x6A): MAC Address Register 2 ........................................................................................................ 43
Register 107 (0x6B): MAC Address Register 3 ........................................................................................................ 43
Register 108 (0x6C): MAC Address Register 4 ........................................................................................................ 43
Register 109 (0X6D): MAC Address Register 5 ....................................................................................................... 43
MIIM Registers.......................................................................................................................................................... 44
Register 0: MII Control .............................................................................................................................................. 44
Register 1: MII Status ............................................................................................................................................... 44
Register 2: PHYID HIGH........................................................................................................................................... 45
Register 3: PHYID LOW ........................................................................................................................................... 45
Register 4: Advertisement Ability .............................................................................................................................. 45
Register 5: Link Partner Ability ................................................................................................................................. 45
Absolute Maximum Ratings(1) .................................................................................................................................... 46
Operating Ratings(2) .................................................................................................................................................... 46
Electrical Characteristics(4, 5)...................................................................................................................................... 46
Timing Diagrams ......................................................................................................................................................... 48
Reset Circuit Diagram................................................................................................................................................. 53
Selection of Isolation Transformer(1) ......................................................................................................................... 54
Package Information ................................................................................................................................................... 55
www.DataSheet4U.com
September 2008
5 M9999-091508

5 Page





KS8995XA arduino
Micrel, Inc.
KS8995XA
Pin Number
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
Pin Name
PMRXDV
PMRXD3
PMRXD2
PMRXD1
PMRXD0
PMRXER
PCRS
PCOL
SMTXEN
SMTXD3
SMTXD2
SMTXD1
SMTXD0
SMTXER
SMTXC
GNDD
VDDIO
SMRXC
SMRXDV
SMRXD3
SMRXD2
SMRXD1
SMRXD0
SCOL
SCRS
Type(1)
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd
Ipd
Ipd
Ipd
Ipd
Ipd
I/O
Gnd
P
I/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Ipd/O
Port
5
5
5
5
5
5
5
5
Pin Function(2)
PHY[5] MII receive data valid.
PHY[5] MII receive bit 3. Strap option: PD (default) = enable flow
control; PU = disable flow control.
PHY[5] MII receive bit 2. Strap option: PD (default) = disable back
pressure; PU = enable back pressure.
PHY[5] MII receive bit 1. Strap option: PD (default) = drop excessive
collision packets; PU = does not drop excessive collision packets.
PHY[5] MII receive bit 0. Strap option: PD (default) = disable
aggressive back-off algorithm in half-duplex mode; PU = enable for
performance enhancement.
PHY[5] MII receive error. Strap option: PD (default) = packet size
1518/1522 bytes; PU = 1536 bytes.
PHY[5] MII carrier sense/strap option for port 4 only. PD (default) =
force half-duplex if auto-negotiation is disabled or fails. PU = force full-
duplex if auto negotiation is disabled or fails. Refer to Register 76.
PHY[5] MII collision detect/ strap option for port 4 only. PD (default) =
no force flow control, normal operation. PU = force flow control. Refer
to Register 66.
Switch MII transmit enable.
Switch MII transmit bit 3.
Switch MII transmit bit 2.
Switch MII transmit bit 1.
Switch MII transmit bit 0.
Switch MII transmit error.
Switch MII transmit clock. PHY or MAC mode MII.
Digital ground.
3.3V digital VDD for digital I/O circuitry.
Switch MII receive clock. PHY or MAC mode MII.
Switch MII receive data valid.
Switch MII receive bit 3. Strap option: PD (default) = Disable Switch MII
full-duplex flow control; PU = Enable Switch MII full-duplex flow control.
Switch MII receive bit 2. Strap option: PD (default) = Switch MII in full-
duplex mode; PU = Switch MII in half-duplex mode.
Switch MII receive bit 1. Strap option: PD (default) = Switch MII in
100Mbps mode; PU = Switch MII in 10Mbps mode.
Switch MII receive bit 0; Strap option: see “Register 11[1].”
Switch MII collision detect.
Switch mode carrier sense.
Notes:
1. P = Power supply.
I = Input.
O = Output.
I/O = Bidirectional.
Gnd = Ground.
Ipu = Input w/internal pull-up.
Ipd = Input w/internal pull-down.
www.DataSIIpphdue//eOOt4==UIInn.cppouumtt ww//iinntteerrnnaall
pull-down during reset, output pin otherwise.
pull-up during reset, output pin otherwise.
2. PU = Strap pin pull-up.
PD = Strap pull-down.
Otri = Output tristated.
September 2008
11 M9999-091508

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